2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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6 * modification, are permitted provided that the following conditions are
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #ifndef __CPU_SIMPLE_TIMING_HH__
32 #define __CPU_SIMPLE_TIMING_HH__
34 #include "cpu/simple/base.hh"
36 class TimingSimpleCPU : public BaseSimpleCPU
40 struct Params : public BaseSimpleCPU::Params {
43 TimingSimpleCPU(Params *params);
44 virtual ~TimingSimpleCPU();
65 Status status() const { return _status; }
71 class CpuPort : public Port
78 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu)
79 : Port(_name), cpu(_cpu)
84 virtual Tick recvAtomic(Packet *pkt);
86 virtual void recvFunctional(Packet *pkt);
88 virtual void recvStatusChange(Status status);
90 virtual void getDeviceAddressRanges(AddrRangeList &resp,
92 { resp.clear(); snoop.clear(); }
95 class IcachePort : public CpuPort
99 IcachePort(TimingSimpleCPU *_cpu)
100 : CpuPort(_cpu->name() + "-iport", _cpu)
105 virtual bool recvTiming(Packet *pkt);
107 virtual void recvRetry();
110 class DcachePort : public CpuPort
114 DcachePort(TimingSimpleCPU *_cpu)
115 : CpuPort(_cpu->name() + "-dport", _cpu)
120 virtual bool recvTiming(Packet *pkt);
122 virtual void recvRetry();
125 IcachePort icachePort;
126 DcachePort dcachePort;
133 virtual void serialize(std::ostream &os);
134 virtual void unserialize(Checkpoint *cp, const std::string §ion);
136 virtual bool drain(Event *drain_event);
137 virtual void resume();
138 virtual void setMemoryMode(State new_mode);
141 void takeOverFrom(BaseCPU *oldCPU);
143 virtual void activateContext(int thread_num, int delay);
144 virtual void suspendContext(int thread_num);
147 Fault read(Addr addr, T &data, unsigned flags);
150 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
153 void completeIfetch(Packet *);
154 void completeDataAccess(Packet *);
155 void advanceInst(Fault fault);
157 void completeDrain();
160 #endif // __CPU_SIMPLE_TIMING_HH__