2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #ifndef __CPU_SIMPLE_TIMING_HH__
32 #define __CPU_SIMPLE_TIMING_HH__
34 #include "cpu/simple/base.hh"
36 class TimingSimpleCPU : public BaseSimpleCPU
40 struct Params : public BaseSimpleCPU::Params {
43 TimingSimpleCPU(Params *params);
44 virtual ~TimingSimpleCPU();
65 Status status() const { return _status; }
73 class CpuPort : public Port
81 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
82 : Port(_name, _cpu), cpu(_cpu), lat(_lat)
89 virtual Tick recvAtomic(PacketPtr pkt);
91 virtual void recvFunctional(PacketPtr pkt);
93 virtual void recvStatusChange(Status status);
95 virtual void getDeviceAddressRanges(AddrRangeList &resp,
97 { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
99 struct TickEvent : public Event
102 TimingSimpleCPU *cpu;
104 TickEvent(TimingSimpleCPU *_cpu)
105 :Event(&mainEventQueue), cpu(_cpu) {}
106 const char *description() { return "Timing CPU clock event"; }
107 void schedule(PacketPtr _pkt, Tick t);
112 class IcachePort : public CpuPort
116 IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
117 : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
122 virtual bool recvTiming(PacketPtr pkt);
124 virtual void recvRetry();
126 struct ITickEvent : public TickEvent
129 ITickEvent(TimingSimpleCPU *_cpu)
132 const char *description() { return "Timing CPU clock event"; }
135 ITickEvent tickEvent;
139 class DcachePort : public CpuPort
143 DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
144 : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
147 virtual void setPeer(Port *port);
151 virtual bool recvTiming(PacketPtr pkt);
153 virtual void recvRetry();
155 struct DTickEvent : public TickEvent
157 DTickEvent(TimingSimpleCPU *_cpu)
160 const char *description() { return "Timing CPU clock event"; }
163 DTickEvent tickEvent;
167 IcachePort icachePort;
168 DcachePort dcachePort;
170 PacketPtr ifetch_pkt;
171 PacketPtr dcache_pkt;
178 virtual Port *getPort(const std::string &if_name, int idx = -1);
180 virtual void serialize(std::ostream &os);
181 virtual void unserialize(Checkpoint *cp, const std::string §ion);
183 virtual unsigned int drain(Event *drain_event);
184 virtual void resume();
187 void takeOverFrom(BaseCPU *oldCPU);
189 virtual void activateContext(int thread_num, int delay);
190 virtual void suspendContext(int thread_num);
193 Fault read(Addr addr, T &data, unsigned flags);
196 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
199 void completeIfetch(PacketPtr );
200 void completeDataAccess(PacketPtr );
201 void advanceInst(Fault fault);
203 void completeDrain();
206 #endif // __CPU_SIMPLE_TIMING_HH__