src/cpu/simple/timing.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #ifndef __CPU_SIMPLE_TIMING_HH__
  32 #define __CPU_SIMPLE_TIMING_HH__
  33
  34 #include "cpu/simple/base.hh"
  35
  36 #include "params/TimingSimpleCPU.hh"
  37
  38 class TimingSimpleCPU : public BaseSimpleCPU
  39 {
  40   public:
  41
  42     TimingSimpleCPU(TimingSimpleCPUParams * params);
  43     virtual ~TimingSimpleCPU();
  44
  45     virtual void init();
  46
  47   public:
  48     Event *drainEvent;
  49
  50   private:
  51
  52     class CpuPort : public Port
  53     {
  54       protected:
  55         TimingSimpleCPU *cpu;
  56         Tick lat;
  57
  58       public:
  59
  60         CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
  61             : Port(_name, _cpu), cpu(_cpu), lat(_lat)
  62         { }
  63
  64         bool snoopRangeSent;
  65
  66       protected:
  67
  68         virtual Tick recvAtomic(PacketPtr pkt);
  69
  70         virtual void recvFunctional(PacketPtr pkt);
  71
  72         virtual void recvStatusChange(Status status);
  73
  74         virtual void getDeviceAddressRanges(AddrRangeList &resp,
  75                                             bool &snoop)
  76         { resp.clear(); snoop = false; }
  77
  78         struct TickEvent : public Event
  79         {
  80             PacketPtr pkt;
  81             TimingSimpleCPU *cpu;
  82
  83             TickEvent(TimingSimpleCPU *_cpu)
  84                 :Event(&mainEventQueue), cpu(_cpu) {}
  85             const char *description() const { return "Timing CPU tick"; }
  86             void schedule(PacketPtr _pkt, Tick t);
  87         };
  88
  89     };
  90
  91     class IcachePort : public CpuPort
  92     {
  93       public:
  94
  95         IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
  96             : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
  97         { }
  98
  99       protected:
 100
 101         virtual bool recvTiming(PacketPtr pkt);
 102
 103         virtual void recvRetry();
 104
 105         struct ITickEvent : public TickEvent
 106         {
 107
 108             ITickEvent(TimingSimpleCPU *_cpu)
 109                 : TickEvent(_cpu) {}
 110             void process();
 111             const char *description() const { return "Timing CPU icache tick"; }
 112         };
 113
 114         ITickEvent tickEvent;
 115
 116     };
 117
 118     class DcachePort : public CpuPort
 119     {
 120       public:
 121
 122         DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
 123             : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
 124         { }
 125
 126         virtual void setPeer(Port *port);
 127
 128       protected:
 129
 130         virtual bool recvTiming(PacketPtr pkt);
 131
 132         virtual void recvRetry();
 133
 134         struct DTickEvent : public TickEvent
 135         {
 136             DTickEvent(TimingSimpleCPU *_cpu)
 137                 : TickEvent(_cpu) {}
 138             void process();
 139             const char *description() const { return "Timing CPU dcache tick"; }
 140         };
 141
 142         DTickEvent tickEvent;
 143
 144     };
 145
 146     IcachePort icachePort;
 147     DcachePort dcachePort;
 148
 149     PacketPtr ifetch_pkt;
 150     PacketPtr dcache_pkt;
 151
 152     Tick previousTick;
 153
 154   public:
 155
 156     virtual Port *getPort(const std::string &if_name, int idx = -1);
 157
 158     virtual void serialize(std::ostream &os);
 159     virtual void unserialize(Checkpoint *cp, const std::string &section);
 160
 161     virtual unsigned int drain(Event *drain_event);
 162     virtual void resume();
 163
 164     void switchOut();
 165     void takeOverFrom(BaseCPU *oldCPU);
 166
 167     virtual void activateContext(int thread_num, int delay);
 168     virtual void suspendContext(int thread_num);
 169
 170     template <class T>
 171     Fault read(Addr addr, T &data, unsigned flags);
 172
 173     Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
 174             int size, unsigned flags);
 175
 176     template <class T>
 177     Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 178
 179     Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
 180             int size, unsigned flags);
 181
 182     void fetch();
 183     void completeIfetch(PacketPtr );
 184     void completeDataAccess(PacketPtr );
 185     void advanceInst(Fault fault);
 186
 187     /**
 188      * Print state of address in memory system via PrintReq (for
 189      * debugging).
 190      */
 191     void printAddr(Addr a);
 192
 193   private:
 194
 195     typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
 196     FetchEvent *fetchEvent;
 197
 198     struct IprEvent : Event {
 199         Packet *pkt;
 200         TimingSimpleCPU *cpu;
 201         IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
 202         virtual void process();
 203         virtual const char *description() const;
 204     };
 205
 206     void completeDrain();
 207 };
 208
 209 #endif // __CPU_SIMPLE_TIMING_HH__