src/cpu/simple_thread.cc

   1 /*
   2  * Copyright (c) 2018 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Steve Reinhardt
  41  *          Nathan Binkert
  42  *          Lisa Hsu
  43  *          Kevin Lim
  44  */
  45
  46 #include "cpu/simple_thread.hh"
  47
  48 #include <string>
  49
  50 #include "arch/isa_traits.hh"
  51 #include "arch/kernel_stats.hh"
  52 #include "arch/stacktrace.hh"
  53 #include "arch/utility.hh"
  54 #include "base/callback.hh"
  55 #include "base/cprintf.hh"
  56 #include "base/output.hh"
  57 #include "base/trace.hh"
  58 #include "config/the_isa.hh"
  59 #include "cpu/base.hh"
  60 #include "cpu/profile.hh"
  61 #include "cpu/quiesce_event.hh"
  62 #include "cpu/thread_context.hh"
  63 #include "mem/fs_translating_port_proxy.hh"
  64 #include "mem/se_translating_port_proxy.hh"
  65 #include "params/BaseCPU.hh"
  66 #include "sim/faults.hh"
  67 #include "sim/full_system.hh"
  68 #include "sim/process.hh"
  69 #include "sim/serialize.hh"
  70 #include "sim/sim_exit.hh"
  71 #include "sim/system.hh"
  72
  73 using namespace std;
  74
  75 // constructor
  76 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
  77                            Process *_process, BaseTLB *_itb,
  78                            BaseTLB *_dtb, TheISA::ISA *_isa)
  79     : ThreadState(_cpu, _thread_num, _process), isa(_isa),
  80       predicate(true), memAccPredicate(true), system(_sys),
  81       itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
  82 {
  83     clearArchRegs();
  84     quiesceEvent = new EndQuiesceEvent(this);
  85 }
  86
  87 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
  88                            BaseTLB *_itb, BaseTLB *_dtb,
  89                            TheISA::ISA *_isa, bool use_kernel_stats)
  90     : ThreadState(_cpu, _thread_num, NULL), isa(_isa),
  91       predicate(true), memAccPredicate(true), system(_sys),
  92       itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
  93 {
  94     quiesceEvent = new EndQuiesceEvent(this);
  95
  96     clearArchRegs();
  97
  98     if (baseCpu->params()->profile) {
  99         profile = new FunctionProfile(system->kernelSymtab);
 100         Callback *cb =
 101             new MakeCallback<SimpleThread,
 102             &SimpleThread::dumpFuncProfile>(this);
 103         registerExitCallback(cb);
 104     }
 105
 106     // let's fill with a dummy node for now so we don't get a segfault
 107     // on the first cycle when there's no node available.
 108     static ProfileNode dummyNode;
 109     profileNode = &dummyNode;
 110     profilePC = 3;
 111
 112     if (use_kernel_stats)
 113         kernelStats = new TheISA::Kernel::Statistics();
 114 }
 115
 116 void
 117 SimpleThread::takeOverFrom(ThreadContext *oldContext)
 118 {
 119     ::takeOverFrom(*this, *oldContext);
 120     decoder.takeOverFrom(oldContext->getDecoderPtr());
 121
 122     kernelStats = oldContext->getKernelStats();
 123     funcExeInst = oldContext->readFuncExeInst();
 124     storeCondFailures = 0;
 125 }
 126
 127 void
 128 SimpleThread::copyState(ThreadContext *oldContext)
 129 {
 130     // copy over functional state
 131     _status = oldContext->status();
 132     copyArchRegs(oldContext);
 133     if (FullSystem)
 134         funcExeInst = oldContext->readFuncExeInst();
 135
 136     _threadId = oldContext->threadId();
 137     _contextId = oldContext->contextId();
 138 }
 139
 140 void
 141 SimpleThread::serialize(CheckpointOut &cp) const
 142 {
 143     ThreadState::serialize(cp);
 144     ::serialize(*this, cp);
 145 }
 146
 147
 148 void
 149 SimpleThread::unserialize(CheckpointIn &cp)
 150 {
 151     ThreadState::unserialize(cp);
 152     ::unserialize(*this, cp);
 153 }
 154
 155 void
 156 SimpleThread::startup()
 157 {
 158     isa->startup(this);
 159 }
 160
 161 void
 162 SimpleThread::dumpFuncProfile()
 163 {
 164     OutputStream *os(simout.create(csprintf("profile.%s.dat", baseCpu->name())));
 165     profile->dump(this, *os->stream());
 166     simout.close(os);
 167 }
 168
 169 void
 170 SimpleThread::activate()
 171 {
 172     if (status() == ThreadContext::Active)
 173         return;
 174
 175     lastActivate = curTick();
 176     _status = ThreadContext::Active;
 177     baseCpu->activateContext(_threadId);
 178 }
 179
 180 void
 181 SimpleThread::suspend()
 182 {
 183     if (status() == ThreadContext::Suspended)
 184         return;
 185
 186     lastActivate = curTick();
 187     lastSuspend = curTick();
 188     _status = ThreadContext::Suspended;
 189     baseCpu->suspendContext(_threadId);
 190 }
 191
 192
 193 void
 194 SimpleThread::halt()
 195 {
 196     if (status() == ThreadContext::Halted)
 197         return;
 198
 199     _status = ThreadContext::Halted;
 200     baseCpu->haltContext(_threadId);
 201 }
 202
 203
 204 void
 205 SimpleThread::regStats(const string &name)
 206 {
 207     if (FullSystem && kernelStats)
 208         kernelStats->regStats(name + ".kern");
 209 }
 210
 211 void
 212 SimpleThread::copyArchRegs(ThreadContext *src_tc)
 213 {
 214     TheISA::copyRegs(src_tc, this);
 215 }