changes regarding fs.py
[gem5.git] / src / cpu / simple_thread.cc
1 /*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34 #include <string>
35
36 #include "arch/isa_traits.hh"
37 #include "cpu/base.hh"
38 #include "cpu/simple_thread.hh"
39 #include "cpu/thread_context.hh"
40
41 #if FULL_SYSTEM
42 #include "base/callback.hh"
43 #include "base/cprintf.hh"
44 #include "base/output.hh"
45 #include "base/trace.hh"
46 #include "cpu/profile.hh"
47 #include "cpu/quiesce_event.hh"
48 #include "kern/kernel_stats.hh"
49 #include "sim/serialize.hh"
50 #include "sim/sim_exit.hh"
51 #include "arch/stacktrace.hh"
52 #else
53 #include "sim/process.hh"
54 #include "sim/system.hh"
55 #include "mem/translating_port.hh"
56 #endif
57
58 using namespace std;
59
60 // constructor
61 #if FULL_SYSTEM
62 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
63 AlphaITB *_itb, AlphaDTB *_dtb,
64 bool use_kernel_stats)
65 : ThreadState(-1, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
66 dtb(_dtb)
67
68 {
69 tc = new ProxyThreadContext<SimpleThread>(this);
70
71 quiesceEvent = new EndQuiesceEvent(tc);
72
73 regs.clear();
74
75 if (cpu->params->profile) {
76 profile = new FunctionProfile(system->kernelSymtab);
77 Callback *cb =
78 new MakeCallback<SimpleThread,
79 &SimpleThread::dumpFuncProfile>(this);
80 registerExitCallback(cb);
81 }
82
83 // let's fill with a dummy node for now so we don't get a segfault
84 // on the first cycle when there's no node available.
85 static ProfileNode dummyNode;
86 profileNode = &dummyNode;
87 profilePC = 3;
88
89 if (use_kernel_stats) {
90 kernelStats = new Kernel::Statistics(system);
91 } else {
92 kernelStats = NULL;
93 }
94 Port *mem_port;
95 physPort = new FunctionalPort(csprintf("%s-%d-funcport",
96 cpu->name(), tid));
97 mem_port = system->physmem->getPort("functional");
98 mem_port->setPeer(physPort);
99 physPort->setPeer(mem_port);
100
101 virtPort = new VirtualPort(csprintf("%s-%d-vport",
102 cpu->name(), tid));
103 mem_port = system->physmem->getPort("functional");
104 mem_port->setPeer(virtPort);
105 virtPort->setPeer(mem_port);
106 }
107 #else
108 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num,
109 Process *_process, int _asid, MemObject* memobj)
110 : ThreadState(-1, _thread_num, _process, _asid, memobj),
111 cpu(_cpu)
112 {
113 /* Use this port to for syscall emulation writes to memory. */
114 Port *mem_port;
115 port = new TranslatingPort(csprintf("%s-%d-funcport",
116 cpu->name(), tid),
117 process->pTable, false);
118 mem_port = memobj->getPort("functional");
119 mem_port->setPeer(port);
120 port->setPeer(mem_port);
121
122 regs.clear();
123 tc = new ProxyThreadContext<SimpleThread>(this);
124 }
125
126 #endif
127
128 SimpleThread::SimpleThread()
129 #if FULL_SYSTEM
130 : ThreadState(-1, -1)
131 #else
132 : ThreadState(-1, -1, NULL, -1, NULL)
133 #endif
134 {
135 tc = new ProxyThreadContext<SimpleThread>(this);
136 regs.clear();
137 }
138
139 SimpleThread::~SimpleThread()
140 {
141 delete tc;
142 }
143
144 void
145 SimpleThread::takeOverFrom(ThreadContext *oldContext)
146 {
147 // some things should already be set up
148 #if FULL_SYSTEM
149 assert(system == oldContext->getSystemPtr());
150 #else
151 assert(process == oldContext->getProcessPtr());
152 #endif
153
154 copyState(oldContext);
155 #if FULL_SYSTEM
156 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
157 if (quiesce) {
158 // Point the quiesce event's TC at this TC so that it wakes up
159 // the proper CPU.
160 quiesce->tc = tc;
161 }
162 if (quiesceEvent) {
163 quiesceEvent->tc = tc;
164 }
165
166 Kernel::Statistics *stats = oldContext->getKernelStats();
167 if (stats) {
168 kernelStats = stats;
169 }
170 #endif
171
172 storeCondFailures = 0;
173
174 oldContext->setStatus(ThreadContext::Unallocated);
175 }
176
177 void
178 SimpleThread::copyTC(ThreadContext *context)
179 {
180 copyState(context);
181
182 #if FULL_SYSTEM
183 EndQuiesceEvent *quiesce = context->getQuiesceEvent();
184 if (quiesce) {
185 quiesceEvent = quiesce;
186 }
187 Kernel::Statistics *stats = context->getKernelStats();
188 if (stats) {
189 kernelStats = stats;
190 }
191 #endif
192 }
193
194 void
195 SimpleThread::copyState(ThreadContext *oldContext)
196 {
197 // copy over functional state
198 _status = oldContext->status();
199 copyArchRegs(oldContext);
200 cpuId = oldContext->readCpuId();
201 #if !FULL_SYSTEM
202 funcExeInst = oldContext->readFuncExeInst();
203 #endif
204 inst = oldContext->getInst();
205 }
206
207 void
208 SimpleThread::serialize(ostream &os)
209 {
210 ThreadState::serialize(os);
211 regs.serialize(os);
212 // thread_num and cpu_id are deterministic from the config
213 }
214
215
216 void
217 SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
218 {
219 ThreadState::unserialize(cp, section);
220 regs.unserialize(cp, section);
221 // thread_num and cpu_id are deterministic from the config
222 }
223
224 #if FULL_SYSTEM
225 void
226 SimpleThread::dumpFuncProfile()
227 {
228 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
229 profile->dump(tc, *os);
230 }
231 #endif
232
233 void
234 SimpleThread::activate(int delay)
235 {
236 if (status() == ThreadContext::Active)
237 return;
238
239 lastActivate = curTick;
240
241 if (status() == ThreadContext::Unallocated) {
242 cpu->activateWhenReady(tid);
243 return;
244 }
245
246 _status = ThreadContext::Active;
247
248 // status() == Suspended
249 cpu->activateContext(tid, delay);
250 }
251
252 void
253 SimpleThread::suspend()
254 {
255 if (status() == ThreadContext::Suspended)
256 return;
257
258 lastActivate = curTick;
259 lastSuspend = curTick;
260 /*
261 #if FULL_SYSTEM
262 // Don't change the status from active if there are pending interrupts
263 if (cpu->check_interrupts()) {
264 assert(status() == ThreadContext::Active);
265 return;
266 }
267 #endif
268 */
269 _status = ThreadContext::Suspended;
270 cpu->suspendContext(tid);
271 }
272
273 void
274 SimpleThread::deallocate()
275 {
276 if (status() == ThreadContext::Unallocated)
277 return;
278
279 _status = ThreadContext::Unallocated;
280 cpu->deallocateContext(tid);
281 }
282
283 void
284 SimpleThread::halt()
285 {
286 if (status() == ThreadContext::Halted)
287 return;
288
289 _status = ThreadContext::Halted;
290 cpu->haltContext(tid);
291 }
292
293
294 void
295 SimpleThread::regStats(const string &name)
296 {
297 #if FULL_SYSTEM
298 if (kernelStats)
299 kernelStats->regStats(name + ".kern");
300 #endif
301 }
302
303 void
304 SimpleThread::copyArchRegs(ThreadContext *src_tc)
305 {
306 TheISA::copyRegs(src_tc, tc);
307 }
308
309 #if FULL_SYSTEM
310 VirtualPort*
311 SimpleThread::getVirtPort(ThreadContext *src_tc)
312 {
313 if (!src_tc)
314 return virtPort;
315
316 VirtualPort *vp;
317 Port *mem_port;
318
319 vp = new VirtualPort("tc-vport", src_tc);
320 mem_port = system->physmem->getPort("functional");
321 mem_port->setPeer(vp);
322 vp->setPeer(mem_port);
323 return vp;
324 }
325
326 void
327 SimpleThread::delVirtPort(VirtualPort *vp)
328 {
329 if (vp != virtPort) {
330 delete vp->getPeer();
331 delete vp;
332 }
333 }
334
335
336 #endif
337