inorder: fix squash bug in branch predictor
[gem5.git] / src / cpu / simple_thread.cc
1 /*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34 #include <string>
35
36 #include "arch/isa_traits.hh"
37 #include "config/the_isa.hh"
38 #include "cpu/base.hh"
39 #include "cpu/simple_thread.hh"
40 #include "cpu/thread_context.hh"
41 #include "params/BaseCPU.hh"
42
43 #if FULL_SYSTEM
44 #include "arch/kernel_stats.hh"
45 #include "arch/stacktrace.hh"
46 #include "base/callback.hh"
47 #include "base/cprintf.hh"
48 #include "base/output.hh"
49 #include "base/trace.hh"
50 #include "cpu/profile.hh"
51 #include "cpu/quiesce_event.hh"
52 #include "sim/serialize.hh"
53 #include "sim/sim_exit.hh"
54 #else
55 #include "mem/translating_port.hh"
56 #include "sim/process.hh"
57 #include "sim/system.hh"
58 #endif
59
60 using namespace std;
61
62 // constructor
63 #if FULL_SYSTEM
64 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
65 TheISA::TLB *_itb, TheISA::TLB *_dtb,
66 bool use_kernel_stats)
67 : ThreadState(_cpu, _thread_num),
68 cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb)
69
70 {
71 tc = new ProxyThreadContext<SimpleThread>(this);
72
73 quiesceEvent = new EndQuiesceEvent(tc);
74
75 clearArchRegs();
76
77 if (cpu->params()->profile) {
78 profile = new FunctionProfile(system->kernelSymtab);
79 Callback *cb =
80 new MakeCallback<SimpleThread,
81 &SimpleThread::dumpFuncProfile>(this);
82 registerExitCallback(cb);
83 }
84
85 // let's fill with a dummy node for now so we don't get a segfault
86 // on the first cycle when there's no node available.
87 static ProfileNode dummyNode;
88 profileNode = &dummyNode;
89 profilePC = 3;
90
91 if (use_kernel_stats)
92 kernelStats = new TheISA::Kernel::Statistics(system);
93 }
94 #else
95 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
96 TheISA::TLB *_itb, TheISA::TLB *_dtb)
97 : ThreadState(_cpu, _thread_num, _process),
98 cpu(_cpu), itb(_itb), dtb(_dtb)
99 {
100 clearArchRegs();
101 tc = new ProxyThreadContext<SimpleThread>(this);
102 }
103
104 #endif
105
106 SimpleThread::SimpleThread()
107 #if FULL_SYSTEM
108 : ThreadState(NULL, -1)
109 #else
110 : ThreadState(NULL, -1, NULL)
111 #endif
112 {
113 tc = new ProxyThreadContext<SimpleThread>(this);
114 }
115
116 SimpleThread::~SimpleThread()
117 {
118 #if FULL_SYSTEM
119 delete physPort;
120 delete virtPort;
121 #endif
122 delete tc;
123 }
124
125 void
126 SimpleThread::takeOverFrom(ThreadContext *oldContext)
127 {
128 // some things should already be set up
129 #if FULL_SYSTEM
130 assert(system == oldContext->getSystemPtr());
131 #else
132 assert(process == oldContext->getProcessPtr());
133 #endif
134
135 copyState(oldContext);
136 #if FULL_SYSTEM
137 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
138 if (quiesce) {
139 // Point the quiesce event's TC at this TC so that it wakes up
140 // the proper CPU.
141 quiesce->tc = tc;
142 }
143 if (quiesceEvent) {
144 quiesceEvent->tc = tc;
145 }
146
147 TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
148 if (stats) {
149 kernelStats = stats;
150 }
151 #endif
152
153 storeCondFailures = 0;
154
155 oldContext->setStatus(ThreadContext::Halted);
156 }
157
158 void
159 SimpleThread::copyTC(ThreadContext *context)
160 {
161 copyState(context);
162
163 #if FULL_SYSTEM
164 EndQuiesceEvent *quiesce = context->getQuiesceEvent();
165 if (quiesce) {
166 quiesceEvent = quiesce;
167 }
168 TheISA::Kernel::Statistics *stats = context->getKernelStats();
169 if (stats) {
170 kernelStats = stats;
171 }
172 #endif
173 }
174
175 void
176 SimpleThread::copyState(ThreadContext *oldContext)
177 {
178 // copy over functional state
179 _status = oldContext->status();
180 copyArchRegs(oldContext);
181 #if !FULL_SYSTEM
182 funcExeInst = oldContext->readFuncExeInst();
183 #endif
184 inst = oldContext->getInst();
185
186 _threadId = oldContext->threadId();
187 _contextId = oldContext->contextId();
188 }
189
190 void
191 SimpleThread::serialize(ostream &os)
192 {
193 ThreadState::serialize(os);
194 SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
195 SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
196 SERIALIZE_SCALAR(microPC);
197 SERIALIZE_SCALAR(nextMicroPC);
198 SERIALIZE_SCALAR(PC);
199 SERIALIZE_SCALAR(nextPC);
200 SERIALIZE_SCALAR(nextNPC);
201 // thread_num and cpu_id are deterministic from the config
202
203 //
204 // Now must serialize all the ISA dependent state
205 //
206 isa.serialize(cpu, os);
207 }
208
209
210 void
211 SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
212 {
213 ThreadState::unserialize(cp, section);
214 UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
215 UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
216 UNSERIALIZE_SCALAR(microPC);
217 UNSERIALIZE_SCALAR(nextMicroPC);
218 UNSERIALIZE_SCALAR(PC);
219 UNSERIALIZE_SCALAR(nextPC);
220 UNSERIALIZE_SCALAR(nextNPC);
221 // thread_num and cpu_id are deterministic from the config
222
223 //
224 // Now must unserialize all the ISA dependent state
225 //
226 isa.unserialize(cpu, cp, section);
227 }
228
229 #if FULL_SYSTEM
230 void
231 SimpleThread::dumpFuncProfile()
232 {
233 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
234 profile->dump(tc, *os);
235 }
236 #endif
237
238 void
239 SimpleThread::activate(int delay)
240 {
241 if (status() == ThreadContext::Active)
242 return;
243
244 lastActivate = curTick;
245
246 // if (status() == ThreadContext::Unallocated) {
247 // cpu->activateWhenReady(_threadId);
248 // return;
249 // }
250
251 _status = ThreadContext::Active;
252
253 // status() == Suspended
254 cpu->activateContext(_threadId, delay);
255 }
256
257 void
258 SimpleThread::suspend()
259 {
260 if (status() == ThreadContext::Suspended)
261 return;
262
263 lastActivate = curTick;
264 lastSuspend = curTick;
265 /*
266 #if FULL_SYSTEM
267 // Don't change the status from active if there are pending interrupts
268 if (cpu->checkInterrupts()) {
269 assert(status() == ThreadContext::Active);
270 return;
271 }
272 #endif
273 */
274 _status = ThreadContext::Suspended;
275 cpu->suspendContext(_threadId);
276 }
277
278
279 void
280 SimpleThread::halt()
281 {
282 if (status() == ThreadContext::Halted)
283 return;
284
285 _status = ThreadContext::Halted;
286 cpu->haltContext(_threadId);
287 }
288
289
290 void
291 SimpleThread::regStats(const string &name)
292 {
293 #if FULL_SYSTEM
294 if (kernelStats)
295 kernelStats->regStats(name + ".kern");
296 #endif
297 }
298
299 void
300 SimpleThread::copyArchRegs(ThreadContext *src_tc)
301 {
302 TheISA::copyRegs(src_tc, tc);
303 }
304