2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
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9 * redistributions in binary form must reproduce the above copyright
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
36 #include "arch/isa_traits.hh"
37 #include "arch/kernel_stats.hh"
38 #include "arch/stacktrace.hh"
39 #include "arch/utility.hh"
40 #include "base/callback.hh"
41 #include "base/cprintf.hh"
42 #include "base/output.hh"
43 #include "base/trace.hh"
44 #include "config/the_isa.hh"
45 #include "cpu/base.hh"
46 #include "cpu/profile.hh"
47 #include "cpu/quiesce_event.hh"
48 #include "cpu/simple_thread.hh"
49 #include "cpu/thread_context.hh"
50 #include "mem/fs_translating_port_proxy.hh"
51 #include "mem/se_translating_port_proxy.hh"
52 #include "params/BaseCPU.hh"
53 #include "sim/full_system.hh"
54 #include "sim/process.hh"
55 #include "sim/serialize.hh"
56 #include "sim/sim_exit.hh"
57 #include "sim/system.hh"
62 SimpleThread::SimpleThread(BaseCPU
*_cpu
, int _thread_num
, System
*_sys
,
63 Process
*_process
, TheISA::TLB
*_itb
,
65 : ThreadState(_cpu
, _thread_num
, _process
), system(_sys
), itb(_itb
),
66 dtb(_dtb
), decoder(NULL
)
69 tc
= new ProxyThreadContext
<SimpleThread
>(this);
71 SimpleThread::SimpleThread(BaseCPU
*_cpu
, int _thread_num
, System
*_sys
,
72 TheISA::TLB
*_itb
, TheISA::TLB
*_dtb
,
73 bool use_kernel_stats
)
74 : ThreadState(_cpu
, _thread_num
, NULL
), system(_sys
), itb(_itb
), dtb(_dtb
),
77 tc
= new ProxyThreadContext
<SimpleThread
>(this);
79 quiesceEvent
= new EndQuiesceEvent(tc
);
83 if (baseCpu
->params()->profile
) {
84 profile
= new FunctionProfile(system
->kernelSymtab
);
86 new MakeCallback
<SimpleThread
,
87 &SimpleThread::dumpFuncProfile
>(this);
88 registerExitCallback(cb
);
91 // let's fill with a dummy node for now so we don't get a segfault
92 // on the first cycle when there's no node available.
93 static ProfileNode dummyNode
;
94 profileNode
= &dummyNode
;
98 kernelStats
= new TheISA::Kernel::Statistics(system
);
101 SimpleThread::SimpleThread()
102 : ThreadState(NULL
, -1, NULL
), decoder(NULL
)
104 tc
= new ProxyThreadContext
<SimpleThread
>(this);
107 SimpleThread::~SimpleThread()
113 SimpleThread::takeOverFrom(ThreadContext
*oldContext
)
115 // some things should already be set up
117 assert(system
== oldContext
->getSystemPtr());
118 assert(process
== oldContext
->getProcessPtr());
120 copyState(oldContext
);
122 EndQuiesceEvent
*quiesce
= oldContext
->getQuiesceEvent();
124 // Point the quiesce event's TC at this TC so that it wakes up
129 quiesceEvent
->tc
= tc
;
132 TheISA::Kernel::Statistics
*stats
= oldContext
->getKernelStats();
138 storeCondFailures
= 0;
140 oldContext
->setStatus(ThreadContext::Halted
);
144 SimpleThread::copyTC(ThreadContext
*context
)
149 EndQuiesceEvent
*quiesce
= context
->getQuiesceEvent();
151 quiesceEvent
= quiesce
;
153 TheISA::Kernel::Statistics
*stats
= context
->getKernelStats();
161 SimpleThread::copyState(ThreadContext
*oldContext
)
163 // copy over functional state
164 _status
= oldContext
->status();
165 copyArchRegs(oldContext
);
167 funcExeInst
= oldContext
->readFuncExeInst();
169 _threadId
= oldContext
->threadId();
170 _contextId
= oldContext
->contextId();
174 SimpleThread::serialize(ostream
&os
)
176 ThreadState::serialize(os
);
177 SERIALIZE_ARRAY(floatRegs
.i
, TheISA::NumFloatRegs
);
178 SERIALIZE_ARRAY(intRegs
, TheISA::NumIntRegs
);
179 _pcState
.serialize(os
);
180 // thread_num and cpu_id are deterministic from the config
183 // Now must serialize all the ISA dependent state
185 isa
.serialize(baseCpu
, os
);
190 SimpleThread::unserialize(Checkpoint
*cp
, const std::string
§ion
)
192 ThreadState::unserialize(cp
, section
);
193 UNSERIALIZE_ARRAY(floatRegs
.i
, TheISA::NumFloatRegs
);
194 UNSERIALIZE_ARRAY(intRegs
, TheISA::NumIntRegs
);
195 _pcState
.unserialize(cp
, section
);
196 // thread_num and cpu_id are deterministic from the config
199 // Now must unserialize all the ISA dependent state
201 isa
.unserialize(baseCpu
, cp
, section
);
205 SimpleThread::dumpFuncProfile()
207 std::ostream
*os
= simout
.create(csprintf("profile.%s.dat",
209 profile
->dump(tc
, *os
);
213 SimpleThread::activate(int delay
)
215 if (status() == ThreadContext::Active
)
218 lastActivate
= curTick();
220 // if (status() == ThreadContext::Unallocated) {
221 // cpu->activateWhenReady(_threadId);
225 _status
= ThreadContext::Active
;
227 // status() == Suspended
228 baseCpu
->activateContext(_threadId
, delay
);
232 SimpleThread::suspend()
234 if (status() == ThreadContext::Suspended
)
237 lastActivate
= curTick();
238 lastSuspend
= curTick();
239 _status
= ThreadContext::Suspended
;
240 baseCpu
->suspendContext(_threadId
);
247 if (status() == ThreadContext::Halted
)
250 _status
= ThreadContext::Halted
;
251 baseCpu
->haltContext(_threadId
);
256 SimpleThread::regStats(const string
&name
)
258 if (FullSystem
&& kernelStats
)
259 kernelStats
->regStats(name
+ ".kern");
263 SimpleThread::copyArchRegs(ThreadContext
*src_tc
)
265 TheISA::copyRegs(src_tc
, tc
);