src/cpu/simple_thread.cc

   1 /*
   2  * Copyright (c) 2018 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Steve Reinhardt
  41  *          Nathan Binkert
  42  *          Lisa Hsu
  43  *          Kevin Lim
  44  */
  45
  46 #include "cpu/simple_thread.hh"
  47
  48 #include <string>
  49
  50 #include "arch/isa_traits.hh"
  51 #include "arch/kernel_stats.hh"
  52 #include "arch/stacktrace.hh"
  53 #include "arch/utility.hh"
  54 #include "base/callback.hh"
  55 #include "base/cprintf.hh"
  56 #include "base/output.hh"
  57 #include "base/trace.hh"
  58 #include "config/the_isa.hh"
  59 #include "cpu/base.hh"
  60 #include "cpu/profile.hh"
  61 #include "cpu/quiesce_event.hh"
  62 #include "cpu/thread_context.hh"
  63 #include "mem/fs_translating_port_proxy.hh"
  64 #include "mem/se_translating_port_proxy.hh"
  65 #include "params/BaseCPU.hh"
  66 #include "sim/faults.hh"
  67 #include "sim/full_system.hh"
  68 #include "sim/process.hh"
  69 #include "sim/serialize.hh"
  70 #include "sim/sim_exit.hh"
  71 #include "sim/system.hh"
  72
  73 using namespace std;
  74
  75 // constructor
  76 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
  77                            Process *_process, BaseTLB *_itb,
  78                            BaseTLB *_dtb, BaseISA *_isa)
  79     : ThreadState(_cpu, _thread_num, _process),
  80       isa(dynamic_cast<TheISA::ISA *>(_isa)),
  81       predicate(true), memAccPredicate(true),
  82       comInstEventQueue("instruction-based event queue"),
  83       system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(isa))
  84 {
  85     assert(isa);
  86     clearArchRegs();
  87     quiesceEvent = new EndQuiesceEvent(this);
  88 }
  89
  90 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
  91                            BaseTLB *_itb, BaseTLB *_dtb,
  92                            BaseISA *_isa, bool use_kernel_stats)
  93     : ThreadState(_cpu, _thread_num, NULL),
  94       isa(dynamic_cast<TheISA::ISA *>(_isa)),
  95       predicate(true), memAccPredicate(true),
  96       comInstEventQueue("instruction-based event queue"),
  97       system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(isa))
  98 {
  99     assert(isa);
 100
 101     quiesceEvent = new EndQuiesceEvent(this);
 102
 103     clearArchRegs();
 104
 105     if (baseCpu->params()->profile) {
 106         profile = new FunctionProfile(system->kernelSymtab);
 107         Callback *cb =
 108             new MakeCallback<SimpleThread,
 109             &SimpleThread::dumpFuncProfile>(this);
 110         registerExitCallback(cb);
 111     }
 112
 113     // let's fill with a dummy node for now so we don't get a segfault
 114     // on the first cycle when there's no node available.
 115     static ProfileNode dummyNode;
 116     profileNode = &dummyNode;
 117     profilePC = 3;
 118
 119     if (use_kernel_stats)
 120         kernelStats = new TheISA::Kernel::Statistics();
 121 }
 122
 123 void
 124 SimpleThread::takeOverFrom(ThreadContext *oldContext)
 125 {
 126     ::takeOverFrom(*this, *oldContext);
 127     decoder.takeOverFrom(oldContext->getDecoderPtr());
 128
 129     kernelStats = oldContext->getKernelStats();
 130     funcExeInst = oldContext->readFuncExeInst();
 131     storeCondFailures = 0;
 132 }
 133
 134 void
 135 SimpleThread::copyState(ThreadContext *oldContext)
 136 {
 137     // copy over functional state
 138     _status = oldContext->status();
 139     copyArchRegs(oldContext);
 140     if (FullSystem)
 141         funcExeInst = oldContext->readFuncExeInst();
 142
 143     _threadId = oldContext->threadId();
 144     _contextId = oldContext->contextId();
 145 }
 146
 147 void
 148 SimpleThread::serialize(CheckpointOut &cp) const
 149 {
 150     ThreadState::serialize(cp);
 151     ::serialize(*this, cp);
 152 }
 153
 154
 155 void
 156 SimpleThread::unserialize(CheckpointIn &cp)
 157 {
 158     ThreadState::unserialize(cp);
 159     ::unserialize(*this, cp);
 160 }
 161
 162 void
 163 SimpleThread::startup()
 164 {
 165     isa->startup(this);
 166 }
 167
 168 void
 169 SimpleThread::dumpFuncProfile()
 170 {
 171     OutputStream *os(simout.create(csprintf("profile.%s.dat", baseCpu->name())));
 172     profile->dump(this, *os->stream());
 173     simout.close(os);
 174 }
 175
 176 void
 177 SimpleThread::activate()
 178 {
 179     if (status() == ThreadContext::Active)
 180         return;
 181
 182     lastActivate = curTick();
 183     _status = ThreadContext::Active;
 184     baseCpu->activateContext(_threadId);
 185 }
 186
 187 void
 188 SimpleThread::suspend()
 189 {
 190     if (status() == ThreadContext::Suspended)
 191         return;
 192
 193     lastActivate = curTick();
 194     lastSuspend = curTick();
 195     _status = ThreadContext::Suspended;
 196     baseCpu->suspendContext(_threadId);
 197 }
 198
 199
 200 void
 201 SimpleThread::halt()
 202 {
 203     if (status() == ThreadContext::Halted)
 204         return;
 205
 206     _status = ThreadContext::Halted;
 207     baseCpu->haltContext(_threadId);
 208 }
 209
 210
 211 void
 212 SimpleThread::regStats(const string &name)
 213 {
 214     if (FullSystem && kernelStats)
 215         kernelStats->regStats(name + ".kern");
 216 }
 217
 218 void
 219 SimpleThread::copyArchRegs(ThreadContext *src_tc)
 220 {
 221     TheISA::copyRegs(src_tc, this);
 222 }