cpu: Fix O3 uncacheable load that is replayed but misses the TLB
[gem5.git] / src / cpu / simple_thread.cc
1 /*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34 #include <string>
35
36 #include "arch/isa_traits.hh"
37 #include "arch/kernel_stats.hh"
38 #include "arch/stacktrace.hh"
39 #include "arch/utility.hh"
40 #include "base/callback.hh"
41 #include "base/cprintf.hh"
42 #include "base/output.hh"
43 #include "base/trace.hh"
44 #include "config/the_isa.hh"
45 #include "cpu/base.hh"
46 #include "cpu/profile.hh"
47 #include "cpu/quiesce_event.hh"
48 #include "cpu/simple_thread.hh"
49 #include "cpu/thread_context.hh"
50 #include "mem/fs_translating_port_proxy.hh"
51 #include "mem/se_translating_port_proxy.hh"
52 #include "params/BaseCPU.hh"
53 #include "sim/full_system.hh"
54 #include "sim/process.hh"
55 #include "sim/serialize.hh"
56 #include "sim/sim_exit.hh"
57 #include "sim/system.hh"
58
59 using namespace std;
60
61 // constructor
62 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
63 Process *_process, TheISA::TLB *_itb,
64 TheISA::TLB *_dtb, TheISA::ISA *_isa)
65 : ThreadState(_cpu, _thread_num, _process), isa(_isa), system(_sys),
66 itb(_itb), dtb(_dtb)
67 {
68 clearArchRegs();
69 tc = new ProxyThreadContext<SimpleThread>(this);
70 }
71
72 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
73 TheISA::TLB *_itb, TheISA::TLB *_dtb,
74 TheISA::ISA *_isa, bool use_kernel_stats)
75 : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
76 dtb(_dtb)
77 {
78 tc = new ProxyThreadContext<SimpleThread>(this);
79
80 quiesceEvent = new EndQuiesceEvent(tc);
81
82 clearArchRegs();
83
84 if (baseCpu->params()->profile) {
85 profile = new FunctionProfile(system->kernelSymtab);
86 Callback *cb =
87 new MakeCallback<SimpleThread,
88 &SimpleThread::dumpFuncProfile>(this);
89 registerExitCallback(cb);
90 }
91
92 // let's fill with a dummy node for now so we don't get a segfault
93 // on the first cycle when there's no node available.
94 static ProfileNode dummyNode;
95 profileNode = &dummyNode;
96 profilePC = 3;
97
98 if (use_kernel_stats)
99 kernelStats = new TheISA::Kernel::Statistics(system);
100 }
101
102 SimpleThread::~SimpleThread()
103 {
104 delete tc;
105 }
106
107 void
108 SimpleThread::takeOverFrom(ThreadContext *oldContext)
109 {
110 ::takeOverFrom(*tc, *oldContext);
111 decoder.takeOverFrom(oldContext->getDecoderPtr());
112
113 kernelStats = oldContext->getKernelStats();
114 funcExeInst = oldContext->readFuncExeInst();
115 storeCondFailures = 0;
116 }
117
118 void
119 SimpleThread::copyState(ThreadContext *oldContext)
120 {
121 // copy over functional state
122 _status = oldContext->status();
123 copyArchRegs(oldContext);
124 if (FullSystem)
125 funcExeInst = oldContext->readFuncExeInst();
126
127 _threadId = oldContext->threadId();
128 _contextId = oldContext->contextId();
129 }
130
131 void
132 SimpleThread::serialize(ostream &os)
133 {
134 ThreadState::serialize(os);
135 ::serialize(*tc, os);
136 }
137
138
139 void
140 SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
141 {
142 ThreadState::unserialize(cp, section);
143 ::unserialize(*tc, cp, section);
144 }
145
146 void
147 SimpleThread::startup()
148 {
149 isa->startup(tc);
150 }
151
152 void
153 SimpleThread::dumpFuncProfile()
154 {
155 std::ostream *os = simout.create(csprintf("profile.%s.dat",
156 baseCpu->name()));
157 profile->dump(tc, *os);
158 }
159
160 void
161 SimpleThread::activate(Cycles delay)
162 {
163 if (status() == ThreadContext::Active)
164 return;
165
166 lastActivate = curTick();
167
168 // if (status() == ThreadContext::Unallocated) {
169 // cpu->activateWhenReady(_threadId);
170 // return;
171 // }
172
173 _status = ThreadContext::Active;
174
175 // status() == Suspended
176 baseCpu->activateContext(_threadId, delay);
177 }
178
179 void
180 SimpleThread::suspend()
181 {
182 if (status() == ThreadContext::Suspended)
183 return;
184
185 lastActivate = curTick();
186 lastSuspend = curTick();
187 _status = ThreadContext::Suspended;
188 baseCpu->suspendContext(_threadId);
189 }
190
191
192 void
193 SimpleThread::halt()
194 {
195 if (status() == ThreadContext::Halted)
196 return;
197
198 _status = ThreadContext::Halted;
199 baseCpu->haltContext(_threadId);
200 }
201
202
203 void
204 SimpleThread::regStats(const string &name)
205 {
206 if (FullSystem && kernelStats)
207 kernelStats->regStats(name + ".kern");
208 }
209
210 void
211 SimpleThread::copyArchRegs(ThreadContext *src_tc)
212 {
213 TheISA::copyRegs(src_tc, tc);
214 }
215