Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
[gem5.git] / src / cpu / simple_thread.cc
1 /*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Lisa Hsu
31 * Kevin Lim
32 */
33
34 #include <string>
35
36 #include "arch/isa_traits.hh"
37 #include "cpu/base.hh"
38 #include "cpu/simple_thread.hh"
39 #include "cpu/thread_context.hh"
40
41 #if FULL_SYSTEM
42 #include "arch/kernel_stats.hh"
43 #include "base/callback.hh"
44 #include "base/cprintf.hh"
45 #include "base/output.hh"
46 #include "base/trace.hh"
47 #include "cpu/profile.hh"
48 #include "cpu/quiesce_event.hh"
49 #include "sim/serialize.hh"
50 #include "sim/sim_exit.hh"
51 #include "arch/stacktrace.hh"
52 #else
53 #include "sim/process.hh"
54 #include "sim/system.hh"
55 #include "mem/translating_port.hh"
56 #endif
57
58 using namespace std;
59
60 // constructor
61 #if FULL_SYSTEM
62 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
63 TheISA::ITB *_itb, TheISA::DTB *_dtb,
64 bool use_kernel_stats)
65 : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
66 dtb(_dtb)
67
68 {
69 tc = new ProxyThreadContext<SimpleThread>(this);
70
71 quiesceEvent = new EndQuiesceEvent(tc);
72
73 regs.clear();
74
75 if (cpu->params->profile) {
76 profile = new FunctionProfile(system->kernelSymtab);
77 Callback *cb =
78 new MakeCallback<SimpleThread,
79 &SimpleThread::dumpFuncProfile>(this);
80 registerExitCallback(cb);
81 }
82
83 // let's fill with a dummy node for now so we don't get a segfault
84 // on the first cycle when there's no node available.
85 static ProfileNode dummyNode;
86 profileNode = &dummyNode;
87 profilePC = 3;
88
89 if (use_kernel_stats) {
90 kernelStats = new TheISA::Kernel::Statistics(system);
91 } else {
92 kernelStats = NULL;
93 }
94 }
95 #else
96 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num,
97 Process *_process, int _asid)
98 : ThreadState(_cpu, -1, _thread_num, _process, _asid),
99 cpu(_cpu)
100 {
101 regs.clear();
102 tc = new ProxyThreadContext<SimpleThread>(this);
103 }
104
105 #endif
106
107 SimpleThread::SimpleThread()
108 #if FULL_SYSTEM
109 : ThreadState(NULL, -1, -1)
110 #else
111 : ThreadState(NULL, -1, -1, NULL, -1)
112 #endif
113 {
114 tc = new ProxyThreadContext<SimpleThread>(this);
115 regs.clear();
116 }
117
118 SimpleThread::~SimpleThread()
119 {
120 #if FULL_SYSTEM
121 delete physPort;
122 delete virtPort;
123 #endif
124 delete tc;
125 }
126
127 void
128 SimpleThread::takeOverFrom(ThreadContext *oldContext)
129 {
130 // some things should already be set up
131 #if FULL_SYSTEM
132 assert(system == oldContext->getSystemPtr());
133 #else
134 assert(process == oldContext->getProcessPtr());
135 #endif
136
137 copyState(oldContext);
138 #if FULL_SYSTEM
139 EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
140 if (quiesce) {
141 // Point the quiesce event's TC at this TC so that it wakes up
142 // the proper CPU.
143 quiesce->tc = tc;
144 }
145 if (quiesceEvent) {
146 quiesceEvent->tc = tc;
147 }
148
149 TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
150 if (stats) {
151 kernelStats = stats;
152 }
153 #endif
154
155 storeCondFailures = 0;
156
157 oldContext->setStatus(ThreadContext::Unallocated);
158 }
159
160 void
161 SimpleThread::copyTC(ThreadContext *context)
162 {
163 copyState(context);
164
165 #if FULL_SYSTEM
166 EndQuiesceEvent *quiesce = context->getQuiesceEvent();
167 if (quiesce) {
168 quiesceEvent = quiesce;
169 }
170 TheISA::Kernel::Statistics *stats = context->getKernelStats();
171 if (stats) {
172 kernelStats = stats;
173 }
174 #endif
175 }
176
177 void
178 SimpleThread::copyState(ThreadContext *oldContext)
179 {
180 // copy over functional state
181 _status = oldContext->status();
182 copyArchRegs(oldContext);
183 cpuId = oldContext->readCpuId();
184 #if !FULL_SYSTEM
185 funcExeInst = oldContext->readFuncExeInst();
186 #endif
187 inst = oldContext->getInst();
188 }
189
190 void
191 SimpleThread::serialize(ostream &os)
192 {
193 ThreadState::serialize(os);
194 regs.serialize(os);
195 // thread_num and cpu_id are deterministic from the config
196 }
197
198
199 void
200 SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
201 {
202 ThreadState::unserialize(cp, section);
203 regs.unserialize(cp, section);
204 // thread_num and cpu_id are deterministic from the config
205 }
206
207 #if FULL_SYSTEM
208 void
209 SimpleThread::dumpFuncProfile()
210 {
211 std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
212 profile->dump(tc, *os);
213 }
214 #endif
215
216 void
217 SimpleThread::activate(int delay)
218 {
219 if (status() == ThreadContext::Active)
220 return;
221
222 lastActivate = curTick;
223
224 if (status() == ThreadContext::Unallocated) {
225 cpu->activateWhenReady(tid);
226 return;
227 }
228
229 _status = ThreadContext::Active;
230
231 // status() == Suspended
232 cpu->activateContext(tid, delay);
233 }
234
235 void
236 SimpleThread::suspend()
237 {
238 if (status() == ThreadContext::Suspended)
239 return;
240
241 lastActivate = curTick;
242 lastSuspend = curTick;
243 /*
244 #if FULL_SYSTEM
245 // Don't change the status from active if there are pending interrupts
246 if (cpu->check_interrupts()) {
247 assert(status() == ThreadContext::Active);
248 return;
249 }
250 #endif
251 */
252 _status = ThreadContext::Suspended;
253 cpu->suspendContext(tid);
254 }
255
256 void
257 SimpleThread::deallocate()
258 {
259 if (status() == ThreadContext::Unallocated)
260 return;
261
262 _status = ThreadContext::Unallocated;
263 cpu->deallocateContext(tid);
264 }
265
266 void
267 SimpleThread::halt()
268 {
269 if (status() == ThreadContext::Halted)
270 return;
271
272 _status = ThreadContext::Halted;
273 cpu->haltContext(tid);
274 }
275
276
277 void
278 SimpleThread::regStats(const string &name)
279 {
280 #if FULL_SYSTEM
281 if (kernelStats)
282 kernelStats->regStats(name + ".kern");
283 #endif
284 }
285
286 void
287 SimpleThread::copyArchRegs(ThreadContext *src_tc)
288 {
289 TheISA::copyRegs(src_tc, tc);
290 }
291
292 #if FULL_SYSTEM
293 VirtualPort*
294 SimpleThread::getVirtPort(ThreadContext *src_tc)
295 {
296 if (!src_tc)
297 return virtPort;
298
299 VirtualPort *vp = new VirtualPort("tc-vport", src_tc);
300 connectToMemFunc(vp);
301 return vp;
302 }
303
304 void
305 SimpleThread::delVirtPort(VirtualPort *vp)
306 {
307 if (vp != virtPort) {
308 vp->removeConn();
309 delete vp;
310 }
311 }
312
313 #endif
314