2 * Copyright (c) 2011 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2001-2006 The Regents of The University of Michigan
15 * All rights reserved.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Steve Reinhardt
44 #ifndef __CPU_SIMPLE_THREAD_HH__
45 #define __CPU_SIMPLE_THREAD_HH__
47 #include "arch/decoder.hh"
48 #include "arch/isa.hh"
49 #include "arch/isa_traits.hh"
50 #include "arch/registers.hh"
51 #include "arch/tlb.hh"
52 #include "arch/types.hh"
53 #include "base/types.hh"
54 #include "config/the_isa.hh"
55 #include "cpu/thread_context.hh"
56 #include "cpu/thread_state.hh"
57 #include "debug/FloatRegs.hh"
58 #include "debug/IntRegs.hh"
59 #include "mem/page_table.hh"
60 #include "mem/request.hh"
61 #include "sim/byteswap.hh"
62 #include "sim/eventq.hh"
63 #include "sim/process.hh"
64 #include "sim/serialize.hh"
65 #include "sim/system.hh"
70 class FunctionProfile;
80 * The SimpleThread object provides a combination of the ThreadState
81 * object and the ThreadContext interface. It implements the
82 * ThreadContext interface so that a ProxyThreadContext class can be
83 * made using SimpleThread as the template parameter (see
84 * thread_context.hh). It adds to the ThreadState object by adding all
85 * the objects needed for simple functional execution, including a
86 * simple architectural register file, and pointers to the ITB and DTB
87 * in full system mode. For CPU models that do not need more advanced
88 * ways to hold state (i.e. a separate physical register file, or
89 * separate fetch and commit PC's), this SimpleThread class provides
90 * all the necessary state for full architecture-level functional
91 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
95 class SimpleThread : public ThreadState
98 typedef TheISA::MachInst MachInst;
99 typedef TheISA::MiscReg MiscReg;
100 typedef TheISA::FloatReg FloatReg;
101 typedef TheISA::FloatRegBits FloatRegBits;
103 typedef ThreadContext::Status Status;
107 FloatReg f[TheISA::NumFloatRegs];
108 FloatRegBits i[TheISA::NumFloatRegs];
110 TheISA::IntReg intRegs[TheISA::NumIntRegs];
111 TheISA::ISA isa; // one "instance" of the current ISA.
113 TheISA::PCState _pcState;
115 /** Did this instruction execute or is it predicated false */
119 std::string name() const
121 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
124 ProxyThreadContext<SimpleThread> *tc;
131 TheISA::Decoder decoder;
133 // constructor: initialize SimpleThread from given process structure
135 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
136 TheISA::TLB *_itb, TheISA::TLB *_dtb,
137 bool use_kernel_stats = true);
139 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
140 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb);
144 virtual ~SimpleThread();
146 virtual void takeOverFrom(ThreadContext *oldContext);
148 void regStats(const std::string &name);
150 void copyTC(ThreadContext *context);
152 void copyState(ThreadContext *oldContext);
154 void serialize(std::ostream &os);
155 void unserialize(Checkpoint *cp, const std::string §ion);
157 /***************************************************************
158 * SimpleThread functions to provide CPU with access to various
160 **************************************************************/
162 /** Returns the pointer to this SimpleThread's ThreadContext. Used
163 * when a ThreadContext must be passed to objects outside of the
166 ThreadContext *getTC() { return tc; }
168 void demapPage(Addr vaddr, uint64_t asn)
170 itb->demapPage(vaddr, asn);
171 dtb->demapPage(vaddr, asn);
174 void demapInstPage(Addr vaddr, uint64_t asn)
176 itb->demapPage(vaddr, asn);
179 void demapDataPage(Addr vaddr, uint64_t asn)
181 dtb->demapPage(vaddr, asn);
184 void dumpFuncProfile();
188 bool simPalCheck(int palFunc);
190 /*******************************************
191 * ThreadContext interface functions.
192 ******************************************/
194 BaseCPU *getCpuPtr() { return baseCpu; }
196 TheISA::TLB *getITBPtr() { return itb; }
198 TheISA::TLB *getDTBPtr() { return dtb; }
200 CheckerCPU *getCheckerCpuPtr() { return NULL; }
202 TheISA::Decoder *getDecoderPtr() { return &decoder; }
204 System *getSystemPtr() { return system; }
206 Status status() const { return _status; }
208 void setStatus(Status newStatus) { _status = newStatus; }
210 /// Set the status to Active. Optional delay indicates number of
211 /// cycles to wait before beginning execution.
212 void activate(int delay = 1);
214 /// Set the status to Suspended.
217 /// Set the status to Halted.
220 virtual bool misspeculating();
222 void copyArchRegs(ThreadContext *tc);
227 memset(intRegs, 0, sizeof(intRegs));
228 memset(floatRegs.i, 0, sizeof(floatRegs.i));
233 // New accessors for new decoder.
235 uint64_t readIntReg(int reg_idx)
237 int flatIndex = isa.flattenIntIndex(reg_idx);
238 assert(flatIndex < TheISA::NumIntRegs);
239 uint64_t regVal = intRegs[flatIndex];
240 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
241 reg_idx, flatIndex, regVal);
245 FloatReg readFloatReg(int reg_idx)
247 int flatIndex = isa.flattenFloatIndex(reg_idx);
248 assert(flatIndex < TheISA::NumFloatRegs);
249 FloatReg regVal = floatRegs.f[flatIndex];
250 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
251 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
255 FloatRegBits readFloatRegBits(int reg_idx)
257 int flatIndex = isa.flattenFloatIndex(reg_idx);
258 assert(flatIndex < TheISA::NumFloatRegs);
259 FloatRegBits regVal = floatRegs.i[flatIndex];
260 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
261 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
265 void setIntReg(int reg_idx, uint64_t val)
267 int flatIndex = isa.flattenIntIndex(reg_idx);
268 assert(flatIndex < TheISA::NumIntRegs);
269 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
270 reg_idx, flatIndex, val);
271 intRegs[flatIndex] = val;
274 void setFloatReg(int reg_idx, FloatReg val)
276 int flatIndex = isa.flattenFloatIndex(reg_idx);
277 assert(flatIndex < TheISA::NumFloatRegs);
278 floatRegs.f[flatIndex] = val;
279 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
280 reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
283 void setFloatRegBits(int reg_idx, FloatRegBits val)
285 int flatIndex = isa.flattenFloatIndex(reg_idx);
286 assert(flatIndex < TheISA::NumFloatRegs);
287 // XXX: Fix array out of bounds compiler error for gem5.fast
288 // when checkercpu enabled
289 if (flatIndex < TheISA::NumFloatRegs)
290 floatRegs.i[flatIndex] = val;
291 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
292 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
302 pcState(const TheISA::PCState &val)
308 pcStateNoRecord(const TheISA::PCState &val)
316 return _pcState.instAddr();
322 return _pcState.nextInstAddr();
328 return _pcState.microPC();
336 void setPredicate(bool val)
342 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
344 return isa.readMiscRegNoEffect(misc_reg);
348 readMiscReg(int misc_reg, ThreadID tid = 0)
350 return isa.readMiscReg(misc_reg, tc);
354 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
356 return isa.setMiscRegNoEffect(misc_reg, val);
360 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
362 return isa.setMiscReg(misc_reg, val, tc);
366 flattenIntIndex(int reg)
368 return isa.flattenIntIndex(reg);
372 flattenFloatIndex(int reg)
374 return isa.flattenFloatIndex(reg);
377 unsigned readStCondFailures() { return storeCondFailures; }
379 void setStCondFailures(unsigned sc_failures)
380 { storeCondFailures = sc_failures; }
382 void syscall(int64_t callnum)
384 process->syscall(callnum, tc);
389 // for non-speculative execution context, spec_mode is always false
391 SimpleThread::misspeculating()
396 #endif // __CPU_CPU_EXEC_CONTEXT_HH__