2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
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9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #ifndef __CPU_SIMPLE_THREAD_HH__
33 #define __CPU_SIMPLE_THREAD_HH__
35 #include "arch/isa_traits.hh"
36 #include "config/full_system.hh"
37 #include "cpu/thread_context.hh"
38 #include "cpu/thread_state.hh"
39 #include "mem/physical.hh"
40 #include "mem/request.hh"
41 #include "sim/byteswap.hh"
42 #include "sim/eventq.hh"
43 #include "sim/host.hh"
44 #include "sim/serialize.hh"
50 #include "sim/system.hh"
51 #include "arch/tlb.hh"
53 class FunctionProfile;
64 #include "sim/process.hh"
65 #include "mem/page_table.hh"
66 class TranslatingPort;
71 * The SimpleThread object provides a combination of the ThreadState
72 * object and the ThreadContext interface. It implements the
73 * ThreadContext interface so that a ProxyThreadContext class can be
74 * made using SimpleThread as the template parameter (see
75 * thread_context.hh). It adds to the ThreadState object by adding all
76 * the objects needed for simple functional execution, including a
77 * simple architectural register file, and pointers to the ITB and DTB
78 * in full system mode. For CPU models that do not need more advanced
79 * ways to hold state (i.e. a separate physical register file, or
80 * separate fetch and commit PC's), this SimpleThread class provides
81 * all the necessary state for full architecture-level functional
82 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
86 class SimpleThread : public ThreadState
89 typedef TheISA::RegFile RegFile;
90 typedef TheISA::MachInst MachInst;
91 typedef TheISA::MiscRegFile MiscRegFile;
92 typedef TheISA::MiscReg MiscReg;
93 typedef TheISA::FloatReg FloatReg;
94 typedef TheISA::FloatRegBits FloatRegBits;
96 typedef ThreadContext::Status Status;
99 RegFile regs; // correct-path register context
102 // pointer to CPU associated with this SimpleThread
105 ProxyThreadContext<SimpleThread> *tc;
114 // constructor: initialize SimpleThread from given process structure
116 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
117 AlphaITB *_itb, AlphaDTB *_dtb,
118 bool use_kernel_stats = true);
120 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid,
126 virtual ~SimpleThread();
128 virtual void takeOverFrom(ThreadContext *oldContext);
130 void regStats(const std::string &name);
132 void copyTC(ThreadContext *context);
134 void copyState(ThreadContext *oldContext);
136 void serialize(std::ostream &os);
137 void unserialize(Checkpoint *cp, const std::string §ion);
139 /***************************************************************
140 * SimpleThread functions to provide CPU with access to various
141 * state, and to provide address translation methods.
142 **************************************************************/
144 /** Returns the pointer to this SimpleThread's ThreadContext. Used
145 * when a ThreadContext must be passed to objects outside of the
148 ThreadContext *getTC() { return tc; }
151 int getInstAsid() { return regs.instAsid(); }
152 int getDataAsid() { return regs.dataAsid(); }
154 Fault translateInstReq(RequestPtr &req)
156 return itb->translate(req, tc);
159 Fault translateDataReadReq(RequestPtr &req)
161 return dtb->translate(req, tc, false);
164 Fault translateDataWriteReq(RequestPtr &req)
166 return dtb->translate(req, tc, true);
169 void dumpFuncProfile();
171 int readIntrFlag() { return regs.intrflag; }
172 void setIntrFlag(int val) { regs.intrflag = val; }
175 bool simPalCheck(int palFunc);
177 Fault translateInstReq(RequestPtr &req)
179 return process->pTable->translate(req);
182 Fault translateDataReadReq(RequestPtr &req)
184 return process->pTable->translate(req);
187 Fault translateDataWriteReq(RequestPtr &req)
189 return process->pTable->translate(req);
193 /*******************************************
194 * ThreadContext interface functions.
195 ******************************************/
197 BaseCPU *getCpuPtr() { return cpu; }
199 int getThreadNum() { return tid; }
202 System *getSystemPtr() { return system; }
204 AlphaITB *getITBPtr() { return itb; }
206 AlphaDTB *getDTBPtr() { return dtb; }
208 FunctionalPort *getPhysPort() { return physPort; }
210 /** Return a virtual port. If no thread context is specified then a static
211 * port is returned. Otherwise a port is created and returned. It must be
212 * deleted by deleteVirtPort(). */
213 VirtualPort *getVirtPort(ThreadContext *tc);
215 void delVirtPort(VirtualPort *vp);
218 Status status() const { return _status; }
220 void setStatus(Status newStatus) { _status = newStatus; }
222 /// Set the status to Active. Optional delay indicates number of
223 /// cycles to wait before beginning execution.
224 void activate(int delay = 1);
226 /// Set the status to Suspended.
229 /// Set the status to Unallocated.
232 /// Set the status to Halted.
237 Fault read(RequestPtr &req, T &data)
239 #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
240 if (req->flags & LOCKED) {
241 req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
242 req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
247 error = mem->prot_read(req->paddr, data, req->size);
248 data = LittleEndianGuest::gtoh(data);
253 Fault write(RequestPtr &req, T &data)
255 #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
258 // If this is a store conditional, act appropriately
259 if (req->flags & LOCKED) {
262 if (req->flags & UNCACHEABLE) {
263 // Don't update result register (see stq_c in isa_desc)
265 xc->setStCondFailures(0);//Needed? [RGD]
267 bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
268 Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
269 req->result = lock_flag;
271 ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
272 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
273 xc->setStCondFailures(xc->readStCondFailures() + 1);
274 if (((xc->readStCondFailures()) % 100000) == 0) {
275 std::cerr << "Warning: "
276 << xc->readStCondFailures()
277 << " consecutive store conditional failures "
278 << "on cpu " << req->xc->readCpuId()
283 else xc->setStCondFailures(0);
287 // Need to clear any locked flags on other proccessors for
288 // this address. Only do this for succsful Store Conditionals
289 // and all other stores (WH64?). Unsuccessful Store
290 // Conditionals would have returned above, and wouldn't fall
292 for (int i = 0; i < system->execContexts.size(); i++){
293 xc = system->execContexts[i];
294 if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
295 (req->paddr & ~0xf)) {
296 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
301 return mem->prot_write(req->paddr, (T)htog(data), req->size);
304 virtual bool misspeculating();
306 Fault instRead(RequestPtr &req)
308 panic("instRead not implemented");
309 // return funcPhysMem->read(req, inst);
313 void copyArchRegs(ThreadContext *tc);
315 void clearArchRegs() { regs.clear(); }
318 // New accessors for new decoder.
320 uint64_t readIntReg(int reg_idx)
322 return regs.readIntReg(reg_idx);
325 FloatReg readFloatReg(int reg_idx, int width)
327 return regs.readFloatReg(reg_idx, width);
330 FloatReg readFloatReg(int reg_idx)
332 return regs.readFloatReg(reg_idx);
335 FloatRegBits readFloatRegBits(int reg_idx, int width)
337 return regs.readFloatRegBits(reg_idx, width);
340 FloatRegBits readFloatRegBits(int reg_idx)
342 return regs.readFloatRegBits(reg_idx);
345 void setIntReg(int reg_idx, uint64_t val)
347 regs.setIntReg(reg_idx, val);
350 void setFloatReg(int reg_idx, FloatReg val, int width)
352 regs.setFloatReg(reg_idx, val, width);
355 void setFloatReg(int reg_idx, FloatReg val)
357 regs.setFloatReg(reg_idx, val);
360 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
362 regs.setFloatRegBits(reg_idx, val, width);
365 void setFloatRegBits(int reg_idx, FloatRegBits val)
367 regs.setFloatRegBits(reg_idx, val);
372 return regs.readPC();
375 void setPC(uint64_t val)
380 uint64_t readNextPC()
382 return regs.readNextPC();
385 void setNextPC(uint64_t val)
390 uint64_t readNextNPC()
392 return regs.readNextNPC();
395 void setNextNPC(uint64_t val)
397 regs.setNextNPC(val);
400 MiscReg readMiscReg(int misc_reg)
402 return regs.readMiscReg(misc_reg);
405 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
407 return regs.readMiscRegWithEffect(misc_reg, fault, tc);
410 Fault setMiscReg(int misc_reg, const MiscReg &val)
412 return regs.setMiscReg(misc_reg, val);
415 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
417 return regs.setMiscRegWithEffect(misc_reg, val, tc);
420 unsigned readStCondFailures() { return storeCondFailures; }
422 void setStCondFailures(unsigned sc_failures)
423 { storeCondFailures = sc_failures; }
426 bool inPalMode() { return AlphaISA::PcPAL(regs.readPC()); }
430 TheISA::IntReg getSyscallArg(int i)
432 return regs.readIntReg(TheISA::ArgumentReg0 + i);
435 // used to shift args for indirect syscall
436 void setSyscallArg(int i, TheISA::IntReg val)
438 regs.setIntReg(TheISA::ArgumentReg0 + i, val);
441 void setSyscallReturn(SyscallReturn return_value)
443 TheISA::setSyscallReturn(return_value, ®s);
446 void syscall(int64_t callnum)
448 process->syscall(callnum, tc);
452 void changeRegFileContext(TheISA::RegContextParam param,
453 TheISA::RegContextVal val)
455 regs.changeContext(param, val);
460 // for non-speculative execution context, spec_mode is always false
462 SimpleThread::misspeculating()
467 #endif // __CPU_CPU_EXEC_CONTEXT_HH__