src/cpu/simple_thread.hh

   1 /*
   2  * Copyright (c) 2001-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #ifndef __CPU_SIMPLE_THREAD_HH__
  33 #define __CPU_SIMPLE_THREAD_HH__
  34
  35 #include "arch/isa_traits.hh"
  36 #include "config/full_system.hh"
  37 #include "cpu/thread_context.hh"
  38 #include "cpu/thread_state.hh"
  39 #include "mem/physical.hh"
  40 #include "mem/request.hh"
  41 #include "sim/byteswap.hh"
  42 #include "sim/eventq.hh"
  43 #include "sim/host.hh"
  44 #include "sim/serialize.hh"
  45
  46 class BaseCPU;
  47
  48 #if FULL_SYSTEM
  49
  50 #include "sim/system.hh"
  51 #include "arch/tlb.hh"
  52
  53 class FunctionProfile;
  54 class ProfileNode;
  55 class FunctionalPort;
  56 class PhysicalPort;
  57
  58 namespace Kernel {
  59     class Statistics;
  60 };
  61
  62 #else // !FULL_SYSTEM
  63
  64 #include "sim/process.hh"
  65 #include "mem/page_table.hh"
  66 class TranslatingPort;
  67
  68 #endif // FULL_SYSTEM
  69
  70 /**
  71  * The SimpleThread object provides a combination of the ThreadState
  72  * object and the ThreadContext interface. It implements the
  73  * ThreadContext interface so that a ProxyThreadContext class can be
  74  * made using SimpleThread as the template parameter (see
  75  * thread_context.hh). It adds to the ThreadState object by adding all
  76  * the objects needed for simple functional execution, including a
  77  * simple architectural register file, and pointers to the ITB and DTB
  78  * in full system mode. For CPU models that do not need more advanced
  79  * ways to hold state (i.e. a separate physical register file, or
  80  * separate fetch and commit PC's), this SimpleThread class provides
  81  * all the necessary state for full architecture-level functional
  82  * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
  83  * examples.
  84  */
  85
  86 class SimpleThread : public ThreadState
  87 {
  88   protected:
  89     typedef TheISA::RegFile RegFile;
  90     typedef TheISA::MachInst MachInst;
  91     typedef TheISA::MiscRegFile MiscRegFile;
  92     typedef TheISA::MiscReg MiscReg;
  93     typedef TheISA::FloatReg FloatReg;
  94     typedef TheISA::FloatRegBits FloatRegBits;
  95   public:
  96     typedef ThreadContext::Status Status;
  97
  98   protected:
  99     RegFile regs;       // correct-path register context
 100
 101   public:
 102     // pointer to CPU associated with this SimpleThread
 103     BaseCPU *cpu;
 104
 105     ProxyThreadContext<SimpleThread> *tc;
 106
 107     System *system;
 108
 109 #if FULL_SYSTEM
 110     AlphaITB *itb;
 111     AlphaDTB *dtb;
 112 #endif
 113
 114     // constructor: initialize SimpleThread from given process structure
 115 #if FULL_SYSTEM
 116     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
 117                  AlphaITB *_itb, AlphaDTB *_dtb,
 118                  bool use_kernel_stats = true);
 119 #else
 120     SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid,
 121                  MemObject *memobj);
 122 #endif
 123
 124     SimpleThread();
 125
 126     virtual ~SimpleThread();
 127
 128     virtual void takeOverFrom(ThreadContext *oldContext);
 129
 130     void regStats(const std::string &name);
 131
 132     void copyTC(ThreadContext *context);
 133
 134     void copyState(ThreadContext *oldContext);
 135
 136     void serialize(std::ostream &os);
 137     void unserialize(Checkpoint *cp, const std::string &section);
 138
 139     /***************************************************************
 140      *  SimpleThread functions to provide CPU with access to various
 141      *  state, and to provide address translation methods.
 142      **************************************************************/
 143
 144     /** Returns the pointer to this SimpleThread's ThreadContext. Used
 145      *  when a ThreadContext must be passed to objects outside of the
 146      *  CPU.
 147      */
 148     ThreadContext *getTC() { return tc; }
 149
 150 #if FULL_SYSTEM
 151     int getInstAsid() { return regs.instAsid(); }
 152     int getDataAsid() { return regs.dataAsid(); }
 153
 154     Fault translateInstReq(RequestPtr &req)
 155     {
 156         return itb->translate(req, tc);
 157     }
 158
 159     Fault translateDataReadReq(RequestPtr &req)
 160     {
 161         return dtb->translate(req, tc, false);
 162     }
 163
 164     Fault translateDataWriteReq(RequestPtr &req)
 165     {
 166         return dtb->translate(req, tc, true);
 167     }
 168
 169     void dumpFuncProfile();
 170
 171     int readIntrFlag() { return regs.intrflag; }
 172     void setIntrFlag(int val) { regs.intrflag = val; }
 173     Fault hwrei();
 174
 175     bool simPalCheck(int palFunc);
 176 #else
 177     Fault translateInstReq(RequestPtr &req)
 178     {
 179         return process->pTable->translate(req);
 180     }
 181
 182     Fault translateDataReadReq(RequestPtr &req)
 183     {
 184         return process->pTable->translate(req);
 185     }
 186
 187     Fault translateDataWriteReq(RequestPtr &req)
 188     {
 189         return process->pTable->translate(req);
 190     }
 191 #endif
 192
 193     /*******************************************
 194      * ThreadContext interface functions.
 195      ******************************************/
 196
 197     BaseCPU *getCpuPtr() { return cpu; }
 198
 199     int getThreadNum() { return tid; }
 200
 201 #if FULL_SYSTEM
 202     System *getSystemPtr() { return system; }
 203
 204     AlphaITB *getITBPtr() { return itb; }
 205
 206     AlphaDTB *getDTBPtr() { return dtb; }
 207
 208     FunctionalPort *getPhysPort() { return physPort; }
 209
 210     /** Return a virtual port. If no thread context is specified then a static
 211      * port is returned. Otherwise a port is created and returned. It must be
 212      * deleted by deleteVirtPort(). */
 213     VirtualPort *getVirtPort(ThreadContext *tc);
 214
 215     void delVirtPort(VirtualPort *vp);
 216 #endif
 217
 218     Status status() const { return _status; }
 219
 220     void setStatus(Status newStatus) { _status = newStatus; }
 221
 222     /// Set the status to Active.  Optional delay indicates number of
 223     /// cycles to wait before beginning execution.
 224     void activate(int delay = 1);
 225
 226     /// Set the status to Suspended.
 227     void suspend();
 228
 229     /// Set the status to Unallocated.
 230     void deallocate();
 231
 232     /// Set the status to Halted.
 233     void halt();
 234
 235 /*
 236     template <class T>
 237     Fault read(RequestPtr &req, T &data)
 238     {
 239 #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
 240         if (req->flags & LOCKED) {
 241             req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
 242             req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
 243         }
 244 #endif
 245
 246         Fault error;
 247         error = mem->prot_read(req->paddr, data, req->size);
 248         data = LittleEndianGuest::gtoh(data);
 249         return error;
 250     }
 251
 252     template <class T>
 253     Fault write(RequestPtr &req, T &data)
 254     {
 255 #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
 256         ExecContext *xc;
 257
 258         // If this is a store conditional, act appropriately
 259         if (req->flags & LOCKED) {
 260             xc = req->xc;
 261
 262             if (req->flags & UNCACHEABLE) {
 263                 // Don't update result register (see stq_c in isa_desc)
 264                 req->result = 2;
 265                 xc->setStCondFailures(0);//Needed? [RGD]
 266             } else {
 267                 bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
 268                 Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
 269                 req->result = lock_flag;
 270                 if (!lock_flag ||
 271                     ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
 272                     xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
 273                     xc->setStCondFailures(xc->readStCondFailures() + 1);
 274                     if (((xc->readStCondFailures()) % 100000) == 0) {
 275                         std::cerr << "Warning: "
 276                                   << xc->readStCondFailures()
 277                                   << " consecutive store conditional failures "
 278                                   << "on cpu " << req->xc->readCpuId()
 279                                   << std::endl;
 280                     }
 281                     return NoFault;
 282                 }
 283                 else xc->setStCondFailures(0);
 284             }
 285         }
 286
 287         // Need to clear any locked flags on other proccessors for
 288         // this address.  Only do this for succsful Store Conditionals
 289         // and all other stores (WH64?).  Unsuccessful Store
 290         // Conditionals would have returned above, and wouldn't fall
 291         // through.
 292         for (int i = 0; i < system->execContexts.size(); i++){
 293             xc = system->execContexts[i];
 294             if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
 295                 (req->paddr & ~0xf)) {
 296                 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
 297             }
 298         }
 299
 300 #endif
 301         return mem->prot_write(req->paddr, (T)htog(data), req->size);
 302     }
 303 */
 304     virtual bool misspeculating();
 305
 306     Fault instRead(RequestPtr &req)
 307     {
 308         panic("instRead not implemented");
 309         // return funcPhysMem->read(req, inst);
 310         return NoFault;
 311     }
 312
 313     void copyArchRegs(ThreadContext *tc);
 314
 315     void clearArchRegs() { regs.clear(); }
 316
 317     //
 318     // New accessors for new decoder.
 319     //
 320     uint64_t readIntReg(int reg_idx)
 321     {
 322         return regs.readIntReg(reg_idx);
 323     }
 324
 325     FloatReg readFloatReg(int reg_idx, int width)
 326     {
 327         return regs.readFloatReg(reg_idx, width);
 328     }
 329
 330     FloatReg readFloatReg(int reg_idx)
 331     {
 332         return regs.readFloatReg(reg_idx);
 333     }
 334
 335     FloatRegBits readFloatRegBits(int reg_idx, int width)
 336     {
 337         return regs.readFloatRegBits(reg_idx, width);
 338     }
 339
 340     FloatRegBits readFloatRegBits(int reg_idx)
 341     {
 342         return regs.readFloatRegBits(reg_idx);
 343     }
 344
 345     void setIntReg(int reg_idx, uint64_t val)
 346     {
 347         regs.setIntReg(reg_idx, val);
 348     }
 349
 350     void setFloatReg(int reg_idx, FloatReg val, int width)
 351     {
 352         regs.setFloatReg(reg_idx, val, width);
 353     }
 354
 355     void setFloatReg(int reg_idx, FloatReg val)
 356     {
 357         regs.setFloatReg(reg_idx, val);
 358     }
 359
 360     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
 361     {
 362         regs.setFloatRegBits(reg_idx, val, width);
 363     }
 364
 365     void setFloatRegBits(int reg_idx, FloatRegBits val)
 366     {
 367         regs.setFloatRegBits(reg_idx, val);
 368     }
 369
 370     uint64_t readPC()
 371     {
 372         return regs.readPC();
 373     }
 374
 375     void setPC(uint64_t val)
 376     {
 377         regs.setPC(val);
 378     }
 379
 380     uint64_t readNextPC()
 381     {
 382         return regs.readNextPC();
 383     }
 384
 385     void setNextPC(uint64_t val)
 386     {
 387         regs.setNextPC(val);
 388     }
 389
 390     uint64_t readNextNPC()
 391     {
 392         return regs.readNextNPC();
 393     }
 394
 395     void setNextNPC(uint64_t val)
 396     {
 397         regs.setNextNPC(val);
 398     }
 399
 400     MiscReg readMiscReg(int misc_reg)
 401     {
 402         return regs.readMiscReg(misc_reg);
 403     }
 404
 405     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
 406     {
 407         return regs.readMiscRegWithEffect(misc_reg, fault, tc);
 408     }
 409
 410     Fault setMiscReg(int misc_reg, const MiscReg &val)
 411     {
 412         return regs.setMiscReg(misc_reg, val);
 413     }
 414
 415     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 416     {
 417         return regs.setMiscRegWithEffect(misc_reg, val, tc);
 418     }
 419
 420     unsigned readStCondFailures() { return storeCondFailures; }
 421
 422     void setStCondFailures(unsigned sc_failures)
 423     { storeCondFailures = sc_failures; }
 424
 425 #if FULL_SYSTEM
 426     bool inPalMode() { return AlphaISA::PcPAL(regs.readPC()); }
 427 #endif
 428
 429 #if !FULL_SYSTEM
 430     TheISA::IntReg getSyscallArg(int i)
 431     {
 432         return regs.readIntReg(TheISA::ArgumentReg0 + i);
 433     }
 434
 435     // used to shift args for indirect syscall
 436     void setSyscallArg(int i, TheISA::IntReg val)
 437     {
 438         regs.setIntReg(TheISA::ArgumentReg0 + i, val);
 439     }
 440
 441     void setSyscallReturn(SyscallReturn return_value)
 442     {
 443         TheISA::setSyscallReturn(return_value, &regs);
 444     }
 445
 446     void syscall(int64_t callnum)
 447     {
 448         process->syscall(callnum, tc);
 449     }
 450 #endif
 451
 452     void changeRegFileContext(TheISA::RegContextParam param,
 453             TheISA::RegContextVal val)
 454     {
 455         regs.changeContext(param, val);
 456     }
 457 };
 458
 459
 460 // for non-speculative execution context, spec_mode is always false
 461 inline bool
 462 SimpleThread::misspeculating()
 463 {
 464     return false;
 465 }
 466
 467 #endif // __CPU_CPU_EXEC_CONTEXT_HH__