src/cpu/simple_thread.hh

   1 /*
   2  * Copyright (c) 2001-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #ifndef __CPU_SIMPLE_THREAD_HH__
  33 #define __CPU_SIMPLE_THREAD_HH__
  34
  35 #include "arch/isa.hh"
  36 #include "arch/isa_traits.hh"
  37 #include "arch/registers.hh"
  38 #include "arch/tlb.hh"
  39 #include "arch/types.hh"
  40 #include "base/types.hh"
  41 #include "config/full_system.hh"
  42 #include "config/the_isa.hh"
  43 #include "cpu/thread_context.hh"
  44 #include "cpu/thread_state.hh"
  45 #include "mem/request.hh"
  46 #include "sim/byteswap.hh"
  47 #include "sim/eventq.hh"
  48 #include "sim/serialize.hh"
  49
  50 class BaseCPU;
  51
  52 #if FULL_SYSTEM
  53
  54 #include "sim/system.hh"
  55
  56 class FunctionProfile;
  57 class ProfileNode;
  58 class FunctionalPort;
  59 class PhysicalPort;
  60
  61 namespace TheISA {
  62     namespace Kernel {
  63         class Statistics;
  64     };
  65 };
  66
  67 #else // !FULL_SYSTEM
  68
  69 #include "sim/process.hh"
  70 #include "mem/page_table.hh"
  71 class TranslatingPort;
  72
  73 #endif // FULL_SYSTEM
  74
  75 /**
  76  * The SimpleThread object provides a combination of the ThreadState
  77  * object and the ThreadContext interface. It implements the
  78  * ThreadContext interface so that a ProxyThreadContext class can be
  79  * made using SimpleThread as the template parameter (see
  80  * thread_context.hh). It adds to the ThreadState object by adding all
  81  * the objects needed for simple functional execution, including a
  82  * simple architectural register file, and pointers to the ITB and DTB
  83  * in full system mode. For CPU models that do not need more advanced
  84  * ways to hold state (i.e. a separate physical register file, or
  85  * separate fetch and commit PC's), this SimpleThread class provides
  86  * all the necessary state for full architecture-level functional
  87  * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
  88  * examples.
  89  */
  90
  91 class SimpleThread : public ThreadState
  92 {
  93   protected:
  94     typedef TheISA::MachInst MachInst;
  95     typedef TheISA::MiscReg MiscReg;
  96     typedef TheISA::FloatReg FloatReg;
  97     typedef TheISA::FloatRegBits FloatRegBits;
  98   public:
  99     typedef ThreadContext::Status Status;
 100
 101   protected:
 102     union {
 103         FloatReg f[TheISA::NumFloatRegs];
 104         FloatRegBits i[TheISA::NumFloatRegs];
 105     } floatRegs;
 106     TheISA::IntReg intRegs[TheISA::NumIntRegs];
 107     TheISA::ISA isa;    // one "instance" of the current ISA.
 108
 109     /** The current microcode pc for the currently executing macro
 110      * operation.
 111      */
 112     MicroPC microPC;
 113
 114     /** The next microcode pc for the currently executing macro
 115      * operation.
 116      */
 117     MicroPC nextMicroPC;
 118
 119     /** The current pc.
 120      */
 121     Addr PC;
 122
 123     /** The next pc.
 124      */
 125     Addr nextPC;
 126
 127     /** The next next pc.
 128      */
 129     Addr nextNPC;
 130
 131   public:
 132     // pointer to CPU associated with this SimpleThread
 133     BaseCPU *cpu;
 134
 135     ProxyThreadContext<SimpleThread> *tc;
 136
 137     System *system;
 138
 139     TheISA::TLB *itb;
 140     TheISA::TLB *dtb;
 141
 142     // constructor: initialize SimpleThread from given process structure
 143 #if FULL_SYSTEM
 144     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
 145                  TheISA::TLB *_itb, TheISA::TLB *_dtb,
 146                  bool use_kernel_stats = true);
 147 #else
 148     SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
 149                  TheISA::TLB *_itb, TheISA::TLB *_dtb);
 150 #endif
 151
 152     SimpleThread();
 153
 154     virtual ~SimpleThread();
 155
 156     virtual void takeOverFrom(ThreadContext *oldContext);
 157
 158     void regStats(const std::string &name);
 159
 160     void copyTC(ThreadContext *context);
 161
 162     void copyState(ThreadContext *oldContext);
 163
 164     void serialize(std::ostream &os);
 165     void unserialize(Checkpoint *cp, const std::string &section);
 166
 167     /***************************************************************
 168      *  SimpleThread functions to provide CPU with access to various
 169      *  state.
 170      **************************************************************/
 171
 172     /** Returns the pointer to this SimpleThread's ThreadContext. Used
 173      *  when a ThreadContext must be passed to objects outside of the
 174      *  CPU.
 175      */
 176     ThreadContext *getTC() { return tc; }
 177
 178     void demapPage(Addr vaddr, uint64_t asn)
 179     {
 180         itb->demapPage(vaddr, asn);
 181         dtb->demapPage(vaddr, asn);
 182     }
 183
 184     void demapInstPage(Addr vaddr, uint64_t asn)
 185     {
 186         itb->demapPage(vaddr, asn);
 187     }
 188
 189     void demapDataPage(Addr vaddr, uint64_t asn)
 190     {
 191         dtb->demapPage(vaddr, asn);
 192     }
 193
 194 #if FULL_SYSTEM
 195     void dumpFuncProfile();
 196
 197     Fault hwrei();
 198
 199     bool simPalCheck(int palFunc);
 200
 201 #endif
 202
 203     /*******************************************
 204      * ThreadContext interface functions.
 205      ******************************************/
 206
 207     BaseCPU *getCpuPtr() { return cpu; }
 208
 209     TheISA::TLB *getITBPtr() { return itb; }
 210
 211     TheISA::TLB *getDTBPtr() { return dtb; }
 212
 213     System *getSystemPtr() { return system; }
 214
 215 #if FULL_SYSTEM
 216     FunctionalPort *getPhysPort() { return physPort; }
 217
 218     /** Return a virtual port. This port cannot be cached locally in an object.
 219      * After a CPU switch it may point to the wrong memory object which could
 220      * mean stale data.
 221      */
 222     VirtualPort *getVirtPort() { return virtPort; }
 223 #endif
 224
 225     Status status() const { return _status; }
 226
 227     void setStatus(Status newStatus) { _status = newStatus; }
 228
 229     /// Set the status to Active.  Optional delay indicates number of
 230     /// cycles to wait before beginning execution.
 231     void activate(int delay = 1);
 232
 233     /// Set the status to Suspended.
 234     void suspend();
 235
 236     /// Set the status to Halted.
 237     void halt();
 238
 239     virtual bool misspeculating();
 240
 241     Fault instRead(RequestPtr &req)
 242     {
 243         panic("instRead not implemented");
 244         // return funcPhysMem->read(req, inst);
 245         return NoFault;
 246     }
 247
 248     void copyArchRegs(ThreadContext *tc);
 249
 250     void clearArchRegs()
 251     {
 252         microPC = 0;
 253         nextMicroPC = 1;
 254         PC = nextPC = nextNPC = 0;
 255         memset(intRegs, 0, sizeof(intRegs));
 256         memset(floatRegs.i, 0, sizeof(floatRegs.i));
 257     }
 258
 259     //
 260     // New accessors for new decoder.
 261     //
 262     uint64_t readIntReg(int reg_idx)
 263     {
 264         int flatIndex = isa.flattenIntIndex(reg_idx);
 265         assert(flatIndex < TheISA::NumIntRegs);
 266         uint64_t regVal = intRegs[flatIndex];
 267         DPRINTF(IntRegs, "Reading int reg %d as %#x.\n", reg_idx, regVal);
 268         return regVal;
 269     }
 270
 271     FloatReg readFloatReg(int reg_idx)
 272     {
 273         int flatIndex = isa.flattenFloatIndex(reg_idx);
 274         assert(flatIndex < TheISA::NumFloatRegs);
 275         return floatRegs.f[flatIndex];
 276     }
 277
 278     FloatRegBits readFloatRegBits(int reg_idx)
 279     {
 280         int flatIndex = isa.flattenFloatIndex(reg_idx);
 281         assert(flatIndex < TheISA::NumFloatRegs);
 282         return floatRegs.i[flatIndex];
 283     }
 284
 285     void setIntReg(int reg_idx, uint64_t val)
 286     {
 287         int flatIndex = isa.flattenIntIndex(reg_idx);
 288         assert(flatIndex < TheISA::NumIntRegs);
 289         DPRINTF(IntRegs, "Setting int reg %d to %#x.\n", reg_idx, val);
 290         intRegs[flatIndex] = val;
 291     }
 292
 293     void setFloatReg(int reg_idx, FloatReg val)
 294     {
 295         int flatIndex = isa.flattenFloatIndex(reg_idx);
 296         assert(flatIndex < TheISA::NumFloatRegs);
 297         floatRegs.f[flatIndex] = val;
 298     }
 299
 300     void setFloatRegBits(int reg_idx, FloatRegBits val)
 301     {
 302         int flatIndex = isa.flattenFloatIndex(reg_idx);
 303         assert(flatIndex < TheISA::NumFloatRegs);
 304         floatRegs.i[flatIndex] = val;
 305     }
 306
 307     uint64_t readPC()
 308     {
 309         return PC;
 310     }
 311
 312     void setPC(uint64_t val)
 313     {
 314         PC = val;
 315     }
 316
 317     uint64_t readMicroPC()
 318     {
 319         return microPC;
 320     }
 321
 322     void setMicroPC(uint64_t val)
 323     {
 324         microPC = val;
 325     }
 326
 327     uint64_t readNextPC()
 328     {
 329         return nextPC;
 330     }
 331
 332     void setNextPC(uint64_t val)
 333     {
 334         nextPC = val;
 335     }
 336
 337     uint64_t readNextMicroPC()
 338     {
 339         return nextMicroPC;
 340     }
 341
 342     void setNextMicroPC(uint64_t val)
 343     {
 344         nextMicroPC = val;
 345     }
 346
 347     uint64_t readNextNPC()
 348     {
 349 #if ISA_HAS_DELAY_SLOT
 350         return nextNPC;
 351 #else
 352         return nextPC + sizeof(TheISA::MachInst);
 353 #endif
 354     }
 355
 356     void setNextNPC(uint64_t val)
 357     {
 358 #if ISA_HAS_DELAY_SLOT
 359         nextNPC = val;
 360 #endif
 361     }
 362
 363     MiscReg
 364     readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
 365     {
 366         return isa.readMiscRegNoEffect(misc_reg);
 367     }
 368
 369     MiscReg
 370     readMiscReg(int misc_reg, ThreadID tid = 0)
 371     {
 372         return isa.readMiscReg(misc_reg, tc);
 373     }
 374
 375     void
 376     setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
 377     {
 378         return isa.setMiscRegNoEffect(misc_reg, val);
 379     }
 380
 381     void
 382     setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
 383     {
 384         return isa.setMiscReg(misc_reg, val, tc);
 385     }
 386
 387     int
 388     flattenIntIndex(int reg)
 389     {
 390         return isa.flattenIntIndex(reg);
 391     }
 392
 393     int
 394     flattenFloatIndex(int reg)
 395     {
 396         return isa.flattenFloatIndex(reg);
 397     }
 398
 399     unsigned readStCondFailures() { return storeCondFailures; }
 400
 401     void setStCondFailures(unsigned sc_failures)
 402     { storeCondFailures = sc_failures; }
 403
 404 #if !FULL_SYSTEM
 405     void syscall(int64_t callnum)
 406     {
 407         process->syscall(callnum, tc);
 408     }
 409 #endif
 410 };
 411
 412
 413 // for non-speculative execution context, spec_mode is always false
 414 inline bool
 415 SimpleThread::misspeculating()
 416 {
 417     return false;
 418 }
 419
 420 #endif // __CPU_CPU_EXEC_CONTEXT_HH__