src/cpu/simple_thread.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2001-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Steve Reinhardt
  41  *          Nathan Binkert
  42  */
  43
  44 #ifndef __CPU_SIMPLE_THREAD_HH__
  45 #define __CPU_SIMPLE_THREAD_HH__
  46
  47 #include "arch/decoder.hh"
  48 #include "arch/isa.hh"
  49 #include "arch/isa_traits.hh"
  50 #include "arch/registers.hh"
  51 #include "arch/tlb.hh"
  52 #include "arch/types.hh"
  53 #include "base/types.hh"
  54 #include "config/the_isa.hh"
  55 #include "cpu/thread_context.hh"
  56 #include "cpu/thread_state.hh"
  57 #include "debug/FloatRegs.hh"
  58 #include "debug/IntRegs.hh"
  59 #include "mem/page_table.hh"
  60 #include "mem/request.hh"
  61 #include "sim/byteswap.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/process.hh"
  64 #include "sim/serialize.hh"
  65 #include "sim/system.hh"
  66
  67 class BaseCPU;
  68 class CheckerCPU;
  69
  70 class FunctionProfile;
  71 class ProfileNode;
  72
  73 namespace TheISA {
  74     namespace Kernel {
  75         class Statistics;
  76     }
  77 }
  78
  79 /**
  80  * The SimpleThread object provides a combination of the ThreadState
  81  * object and the ThreadContext interface. It implements the
  82  * ThreadContext interface so that a ProxyThreadContext class can be
  83  * made using SimpleThread as the template parameter (see
  84  * thread_context.hh). It adds to the ThreadState object by adding all
  85  * the objects needed for simple functional execution, including a
  86  * simple architectural register file, and pointers to the ITB and DTB
  87  * in full system mode. For CPU models that do not need more advanced
  88  * ways to hold state (i.e. a separate physical register file, or
  89  * separate fetch and commit PC's), this SimpleThread class provides
  90  * all the necessary state for full architecture-level functional
  91  * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
  92  * examples.
  93  */
  94
  95 class SimpleThread : public ThreadState
  96 {
  97   protected:
  98     typedef TheISA::MachInst MachInst;
  99     typedef TheISA::MiscReg MiscReg;
 100     typedef TheISA::FloatReg FloatReg;
 101     typedef TheISA::FloatRegBits FloatRegBits;
 102   public:
 103     typedef ThreadContext::Status Status;
 104
 105   protected:
 106     union {
 107         FloatReg f[TheISA::NumFloatRegs];
 108         FloatRegBits i[TheISA::NumFloatRegs];
 109     } floatRegs;
 110     TheISA::IntReg intRegs[TheISA::NumIntRegs];
 111     TheISA::ISA *const isa;    // one "instance" of the current ISA.
 112
 113     TheISA::PCState _pcState;
 114
 115     /** Did this instruction execute or is it predicated false */
 116     bool predicate;
 117
 118   public:
 119     std::string name() const
 120     {
 121         return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
 122     }
 123
 124     ProxyThreadContext<SimpleThread> *tc;
 125
 126     System *system;
 127
 128     TheISA::TLB *itb;
 129     TheISA::TLB *dtb;
 130
 131     TheISA::Decoder decoder;
 132
 133     // constructor: initialize SimpleThread from given process structure
 134     // FS
 135     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
 136                  TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa,
 137                  bool use_kernel_stats = true);
 138     // SE
 139     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
 140                  Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb,
 141                  TheISA::ISA *_isa);
 142
 143     SimpleThread();
 144
 145     virtual ~SimpleThread();
 146
 147     virtual void takeOverFrom(ThreadContext *oldContext);
 148
 149     void regStats(const std::string &name);
 150
 151     void copyTC(ThreadContext *context);
 152
 153     void copyState(ThreadContext *oldContext);
 154
 155     void serialize(std::ostream &os);
 156     void unserialize(Checkpoint *cp, const std::string &section);
 157
 158     /***************************************************************
 159      *  SimpleThread functions to provide CPU with access to various
 160      *  state.
 161      **************************************************************/
 162
 163     /** Returns the pointer to this SimpleThread's ThreadContext. Used
 164      *  when a ThreadContext must be passed to objects outside of the
 165      *  CPU.
 166      */
 167     ThreadContext *getTC() { return tc; }
 168
 169     void demapPage(Addr vaddr, uint64_t asn)
 170     {
 171         itb->demapPage(vaddr, asn);
 172         dtb->demapPage(vaddr, asn);
 173     }
 174
 175     void demapInstPage(Addr vaddr, uint64_t asn)
 176     {
 177         itb->demapPage(vaddr, asn);
 178     }
 179
 180     void demapDataPage(Addr vaddr, uint64_t asn)
 181     {
 182         dtb->demapPage(vaddr, asn);
 183     }
 184
 185     void dumpFuncProfile();
 186
 187     Fault hwrei();
 188
 189     bool simPalCheck(int palFunc);
 190
 191     /*******************************************
 192      * ThreadContext interface functions.
 193      ******************************************/
 194
 195     BaseCPU *getCpuPtr() { return baseCpu; }
 196
 197     TheISA::TLB *getITBPtr() { return itb; }
 198
 199     TheISA::TLB *getDTBPtr() { return dtb; }
 200
 201     CheckerCPU *getCheckerCpuPtr() { return NULL; }
 202
 203     TheISA::Decoder *getDecoderPtr() { return &decoder; }
 204
 205     System *getSystemPtr() { return system; }
 206
 207     Status status() const { return _status; }
 208
 209     void setStatus(Status newStatus) { _status = newStatus; }
 210
 211     /// Set the status to Active.  Optional delay indicates number of
 212     /// cycles to wait before beginning execution.
 213     void activate(Cycles delay = Cycles(1));
 214
 215     /// Set the status to Suspended.
 216     void suspend();
 217
 218     /// Set the status to Halted.
 219     void halt();
 220
 221     virtual bool misspeculating();
 222
 223     void copyArchRegs(ThreadContext *tc);
 224
 225     void clearArchRegs()
 226     {
 227         _pcState = 0;
 228         memset(intRegs, 0, sizeof(intRegs));
 229         memset(floatRegs.i, 0, sizeof(floatRegs.i));
 230         isa->clear();
 231     }
 232
 233     //
 234     // New accessors for new decoder.
 235     //
 236     uint64_t readIntReg(int reg_idx)
 237     {
 238         int flatIndex = isa->flattenIntIndex(reg_idx);
 239         assert(flatIndex < TheISA::NumIntRegs);
 240         uint64_t regVal(readIntRegFlat(flatIndex));
 241         DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
 242                 reg_idx, flatIndex, regVal);
 243         return regVal;
 244     }
 245
 246     FloatReg readFloatReg(int reg_idx)
 247     {
 248         int flatIndex = isa->flattenFloatIndex(reg_idx);
 249         assert(flatIndex < TheISA::NumFloatRegs);
 250         FloatReg regVal(readFloatRegFlat(flatIndex));
 251         DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
 252                 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
 253         return regVal;
 254     }
 255
 256     FloatRegBits readFloatRegBits(int reg_idx)
 257     {
 258         int flatIndex = isa->flattenFloatIndex(reg_idx);
 259         assert(flatIndex < TheISA::NumFloatRegs);
 260         FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
 261         DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
 262                 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
 263         return regVal;
 264     }
 265
 266     void setIntReg(int reg_idx, uint64_t val)
 267     {
 268         int flatIndex = isa->flattenIntIndex(reg_idx);
 269         assert(flatIndex < TheISA::NumIntRegs);
 270         DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
 271                 reg_idx, flatIndex, val);
 272         setIntRegFlat(flatIndex, val);
 273     }
 274
 275     void setFloatReg(int reg_idx, FloatReg val)
 276     {
 277         int flatIndex = isa->flattenFloatIndex(reg_idx);
 278         assert(flatIndex < TheISA::NumFloatRegs);
 279         setFloatRegFlat(flatIndex, val);
 280         DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
 281                 reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
 282     }
 283
 284     void setFloatRegBits(int reg_idx, FloatRegBits val)
 285     {
 286         int flatIndex = isa->flattenFloatIndex(reg_idx);
 287         assert(flatIndex < TheISA::NumFloatRegs);
 288         // XXX: Fix array out of bounds compiler error for gem5.fast
 289         // when checkercpu enabled
 290         if (flatIndex < TheISA::NumFloatRegs)
 291             setFloatRegBitsFlat(flatIndex, val);
 292         DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
 293                 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
 294     }
 295
 296     TheISA::PCState
 297     pcState()
 298     {
 299         return _pcState;
 300     }
 301
 302     void
 303     pcState(const TheISA::PCState &val)
 304     {
 305         _pcState = val;
 306     }
 307
 308     void
 309     pcStateNoRecord(const TheISA::PCState &val)
 310     {
 311         _pcState = val;
 312     }
 313
 314     Addr
 315     instAddr()
 316     {
 317         return _pcState.instAddr();
 318     }
 319
 320     Addr
 321     nextInstAddr()
 322     {
 323         return _pcState.nextInstAddr();
 324     }
 325
 326     MicroPC
 327     microPC()
 328     {
 329         return _pcState.microPC();
 330     }
 331
 332     bool readPredicate()
 333     {
 334         return predicate;
 335     }
 336
 337     void setPredicate(bool val)
 338     {
 339         predicate = val;
 340     }
 341
 342     MiscReg
 343     readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
 344     {
 345         return isa->readMiscRegNoEffect(misc_reg);
 346     }
 347
 348     MiscReg
 349     readMiscReg(int misc_reg, ThreadID tid = 0)
 350     {
 351         return isa->readMiscReg(misc_reg, tc);
 352     }
 353
 354     void
 355     setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
 356     {
 357         return isa->setMiscRegNoEffect(misc_reg, val);
 358     }
 359
 360     void
 361     setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
 362     {
 363         return isa->setMiscReg(misc_reg, val, tc);
 364     }
 365
 366     int
 367     flattenIntIndex(int reg)
 368     {
 369         return isa->flattenIntIndex(reg);
 370     }
 371
 372     int
 373     flattenFloatIndex(int reg)
 374     {
 375         return isa->flattenFloatIndex(reg);
 376     }
 377
 378     unsigned readStCondFailures() { return storeCondFailures; }
 379
 380     void setStCondFailures(unsigned sc_failures)
 381     { storeCondFailures = sc_failures; }
 382
 383     void syscall(int64_t callnum)
 384     {
 385         process->syscall(callnum, tc);
 386     }
 387
 388     uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
 389     void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
 390
 391     FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; }
 392     void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; }
 393
 394     FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
 395     void setFloatRegBitsFlat(int idx, FloatRegBits val) {
 396         floatRegs.i[idx] = val;
 397     }
 398
 399 };
 400
 401
 402 // for non-speculative execution context, spec_mode is always false
 403 inline bool
 404 SimpleThread::misspeculating()
 405 {
 406     return false;
 407 }
 408
 409 #endif // __CPU_CPU_EXEC_CONTEXT_HH__