src/cpu/simple_thread.hh

   1 /*
   2  * Copyright (c) 2001-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #ifndef __CPU_SIMPLE_THREAD_HH__
  33 #define __CPU_SIMPLE_THREAD_HH__
  34
  35 #include "arch/isa.hh"
  36 #include "arch/isa_traits.hh"
  37 #include "arch/registers.hh"
  38 #include "arch/tlb.hh"
  39 #include "arch/types.hh"
  40 #include "base/types.hh"
  41 #include "config/full_system.hh"
  42 #include "config/the_isa.hh"
  43 #include "cpu/thread_context.hh"
  44 #include "cpu/thread_state.hh"
  45 #include "mem/request.hh"
  46 #include "sim/byteswap.hh"
  47 #include "sim/eventq.hh"
  48 #include "sim/serialize.hh"
  49
  50 class BaseCPU;
  51
  52 #if FULL_SYSTEM
  53
  54 #include "sim/system.hh"
  55
  56 class FunctionProfile;
  57 class ProfileNode;
  58 class FunctionalPort;
  59 class PhysicalPort;
  60
  61 namespace TheISA {
  62     namespace Kernel {
  63         class Statistics;
  64     };
  65 };
  66
  67 #else // !FULL_SYSTEM
  68
  69 #include "mem/page_table.hh"
  70 #include "sim/process.hh"
  71 class TranslatingPort;
  72
  73 #endif // FULL_SYSTEM
  74
  75 /**
  76  * The SimpleThread object provides a combination of the ThreadState
  77  * object and the ThreadContext interface. It implements the
  78  * ThreadContext interface so that a ProxyThreadContext class can be
  79  * made using SimpleThread as the template parameter (see
  80  * thread_context.hh). It adds to the ThreadState object by adding all
  81  * the objects needed for simple functional execution, including a
  82  * simple architectural register file, and pointers to the ITB and DTB
  83  * in full system mode. For CPU models that do not need more advanced
  84  * ways to hold state (i.e. a separate physical register file, or
  85  * separate fetch and commit PC's), this SimpleThread class provides
  86  * all the necessary state for full architecture-level functional
  87  * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
  88  * examples.
  89  */
  90
  91 class SimpleThread : public ThreadState
  92 {
  93   protected:
  94     typedef TheISA::MachInst MachInst;
  95     typedef TheISA::MiscReg MiscReg;
  96     typedef TheISA::FloatReg FloatReg;
  97     typedef TheISA::FloatRegBits FloatRegBits;
  98   public:
  99     typedef ThreadContext::Status Status;
 100
 101   protected:
 102     union {
 103         FloatReg f[TheISA::NumFloatRegs];
 104         FloatRegBits i[TheISA::NumFloatRegs];
 105     } floatRegs;
 106     TheISA::IntReg intRegs[TheISA::NumIntRegs];
 107     TheISA::ISA isa;    // one "instance" of the current ISA.
 108
 109     TheISA::PCState _pcState;
 110
 111     /** Did this instruction execute or is it predicated false */
 112     bool predicate;
 113
 114   public:
 115     // pointer to CPU associated with this SimpleThread
 116     BaseCPU *cpu;
 117
 118     ProxyThreadContext<SimpleThread> *tc;
 119
 120     System *system;
 121
 122     TheISA::TLB *itb;
 123     TheISA::TLB *dtb;
 124
 125     // constructor: initialize SimpleThread from given process structure
 126 #if FULL_SYSTEM
 127     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
 128                  TheISA::TLB *_itb, TheISA::TLB *_dtb,
 129                  bool use_kernel_stats = true);
 130 #else
 131     SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
 132                  TheISA::TLB *_itb, TheISA::TLB *_dtb);
 133 #endif
 134
 135     SimpleThread();
 136
 137     virtual ~SimpleThread();
 138
 139     virtual void takeOverFrom(ThreadContext *oldContext);
 140
 141     void regStats(const std::string &name);
 142
 143     void copyTC(ThreadContext *context);
 144
 145     void copyState(ThreadContext *oldContext);
 146
 147     void serialize(std::ostream &os);
 148     void unserialize(Checkpoint *cp, const std::string &section);
 149
 150     /***************************************************************
 151      *  SimpleThread functions to provide CPU with access to various
 152      *  state.
 153      **************************************************************/
 154
 155     /** Returns the pointer to this SimpleThread's ThreadContext. Used
 156      *  when a ThreadContext must be passed to objects outside of the
 157      *  CPU.
 158      */
 159     ThreadContext *getTC() { return tc; }
 160
 161     void demapPage(Addr vaddr, uint64_t asn)
 162     {
 163         itb->demapPage(vaddr, asn);
 164         dtb->demapPage(vaddr, asn);
 165     }
 166
 167     void demapInstPage(Addr vaddr, uint64_t asn)
 168     {
 169         itb->demapPage(vaddr, asn);
 170     }
 171
 172     void demapDataPage(Addr vaddr, uint64_t asn)
 173     {
 174         dtb->demapPage(vaddr, asn);
 175     }
 176
 177 #if FULL_SYSTEM
 178     void dumpFuncProfile();
 179
 180     Fault hwrei();
 181
 182     bool simPalCheck(int palFunc);
 183
 184 #endif
 185
 186     /*******************************************
 187      * ThreadContext interface functions.
 188      ******************************************/
 189
 190     BaseCPU *getCpuPtr() { return cpu; }
 191
 192     TheISA::TLB *getITBPtr() { return itb; }
 193
 194     TheISA::TLB *getDTBPtr() { return dtb; }
 195
 196     System *getSystemPtr() { return system; }
 197
 198 #if FULL_SYSTEM
 199     FunctionalPort *getPhysPort() { return physPort; }
 200
 201     /** Return a virtual port. This port cannot be cached locally in an object.
 202      * After a CPU switch it may point to the wrong memory object which could
 203      * mean stale data.
 204      */
 205     VirtualPort *getVirtPort() { return virtPort; }
 206 #endif
 207
 208     Status status() const { return _status; }
 209
 210     void setStatus(Status newStatus) { _status = newStatus; }
 211
 212     /// Set the status to Active.  Optional delay indicates number of
 213     /// cycles to wait before beginning execution.
 214     void activate(int delay = 1);
 215
 216     /// Set the status to Suspended.
 217     void suspend();
 218
 219     /// Set the status to Halted.
 220     void halt();
 221
 222     virtual bool misspeculating();
 223
 224     void copyArchRegs(ThreadContext *tc);
 225
 226     void clearArchRegs()
 227     {
 228         _pcState = 0;
 229         memset(intRegs, 0, sizeof(intRegs));
 230         memset(floatRegs.i, 0, sizeof(floatRegs.i));
 231         isa.clear();
 232     }
 233
 234     //
 235     // New accessors for new decoder.
 236     //
 237     uint64_t readIntReg(int reg_idx)
 238     {
 239         int flatIndex = isa.flattenIntIndex(reg_idx);
 240         assert(flatIndex < TheISA::NumIntRegs);
 241         uint64_t regVal = intRegs[flatIndex];
 242         DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
 243                 reg_idx, flatIndex, regVal);
 244         return regVal;
 245     }
 246
 247     FloatReg readFloatReg(int reg_idx)
 248     {
 249         int flatIndex = isa.flattenFloatIndex(reg_idx);
 250         assert(flatIndex < TheISA::NumFloatRegs);
 251         FloatReg regVal = floatRegs.f[flatIndex];
 252         DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
 253                 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
 254         return regVal;
 255     }
 256
 257     FloatRegBits readFloatRegBits(int reg_idx)
 258     {
 259         int flatIndex = isa.flattenFloatIndex(reg_idx);
 260         assert(flatIndex < TheISA::NumFloatRegs);
 261         FloatRegBits regVal = floatRegs.i[flatIndex];
 262         DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
 263                 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
 264         return regVal;
 265     }
 266
 267     void setIntReg(int reg_idx, uint64_t val)
 268     {
 269         int flatIndex = isa.flattenIntIndex(reg_idx);
 270         assert(flatIndex < TheISA::NumIntRegs);
 271         DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
 272                 reg_idx, flatIndex, val);
 273         intRegs[flatIndex] = val;
 274     }
 275
 276     void setFloatReg(int reg_idx, FloatReg val)
 277     {
 278         int flatIndex = isa.flattenFloatIndex(reg_idx);
 279         assert(flatIndex < TheISA::NumFloatRegs);
 280         floatRegs.f[flatIndex] = val;
 281         DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
 282                 reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
 283     }
 284
 285     void setFloatRegBits(int reg_idx, FloatRegBits val)
 286     {
 287         int flatIndex = isa.flattenFloatIndex(reg_idx);
 288         assert(flatIndex < TheISA::NumFloatRegs);
 289         floatRegs.i[flatIndex] = val;
 290         DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
 291                 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
 292     }
 293
 294     TheISA::PCState
 295     pcState()
 296     {
 297         return _pcState;
 298     }
 299
 300     void
 301     pcState(const TheISA::PCState &val)
 302     {
 303         _pcState = val;
 304     }
 305
 306     Addr
 307     instAddr()
 308     {
 309         return _pcState.instAddr();
 310     }
 311
 312     Addr
 313     nextInstAddr()
 314     {
 315         return _pcState.nextInstAddr();
 316     }
 317
 318     MicroPC
 319     microPC()
 320     {
 321         return _pcState.microPC();
 322     }
 323
 324     bool readPredicate()
 325     {
 326         return predicate;
 327     }
 328
 329     void setPredicate(bool val)
 330     {
 331         predicate = val;
 332     }
 333
 334     MiscReg
 335     readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
 336     {
 337         return isa.readMiscRegNoEffect(misc_reg);
 338     }
 339
 340     MiscReg
 341     readMiscReg(int misc_reg, ThreadID tid = 0)
 342     {
 343         return isa.readMiscReg(misc_reg, tc);
 344     }
 345
 346     void
 347     setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
 348     {
 349         return isa.setMiscRegNoEffect(misc_reg, val);
 350     }
 351
 352     void
 353     setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
 354     {
 355         return isa.setMiscReg(misc_reg, val, tc);
 356     }
 357
 358     int
 359     flattenIntIndex(int reg)
 360     {
 361         return isa.flattenIntIndex(reg);
 362     }
 363
 364     int
 365     flattenFloatIndex(int reg)
 366     {
 367         return isa.flattenFloatIndex(reg);
 368     }
 369
 370     unsigned readStCondFailures() { return storeCondFailures; }
 371
 372     void setStCondFailures(unsigned sc_failures)
 373     { storeCondFailures = sc_failures; }
 374
 375 #if !FULL_SYSTEM
 376     void syscall(int64_t callnum)
 377     {
 378         process->syscall(callnum, tc);
 379     }
 380 #endif
 381 };
 382
 383
 384 // for non-speculative execution context, spec_mode is always false
 385 inline bool
 386 SimpleThread::misspeculating()
 387 {
 388     return false;
 389 }
 390
 391 #endif // __CPU_CPU_EXEC_CONTEXT_HH__