src/cpu/simple_thread.hh

   1 /*
   2  * Copyright (c) 2011-2012, 2016 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2001-2006 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Steve Reinhardt
  42  *          Nathan Binkert
  43  */
  44
  45 #ifndef __CPU_SIMPLE_THREAD_HH__
  46 #define __CPU_SIMPLE_THREAD_HH__
  47
  48 #include "arch/decoder.hh"
  49 #include "arch/generic/tlb.hh"
  50 #include "arch/isa.hh"
  51 #include "arch/isa_traits.hh"
  52 #include "arch/registers.hh"
  53 #include "arch/types.hh"
  54 #include "base/types.hh"
  55 #include "config/the_isa.hh"
  56 #include "cpu/thread_context.hh"
  57 #include "cpu/thread_state.hh"
  58 #include "debug/CCRegs.hh"
  59 #include "debug/FloatRegs.hh"
  60 #include "debug/IntRegs.hh"
  61 #include "debug/VecRegs.hh"
  62 #include "mem/page_table.hh"
  63 #include "mem/request.hh"
  64 #include "sim/byteswap.hh"
  65 #include "sim/eventq.hh"
  66 #include "sim/process.hh"
  67 #include "sim/serialize.hh"
  68 #include "sim/system.hh"
  69
  70 class BaseCPU;
  71 class CheckerCPU;
  72
  73 class FunctionProfile;
  74 class ProfileNode;
  75
  76 namespace TheISA {
  77     namespace Kernel {
  78         class Statistics;
  79     }
  80 }
  81
  82 /**
  83  * The SimpleThread object provides a combination of the ThreadState
  84  * object and the ThreadContext interface. It implements the
  85  * ThreadContext interface so that a ProxyThreadContext class can be
  86  * made using SimpleThread as the template parameter (see
  87  * thread_context.hh). It adds to the ThreadState object by adding all
  88  * the objects needed for simple functional execution, including a
  89  * simple architectural register file, and pointers to the ITB and DTB
  90  * in full system mode. For CPU models that do not need more advanced
  91  * ways to hold state (i.e. a separate physical register file, or
  92  * separate fetch and commit PC's), this SimpleThread class provides
  93  * all the necessary state for full architecture-level functional
  94  * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
  95  * examples.
  96  */
  97
  98 class SimpleThread : public ThreadState
  99 {
 100   protected:
 101     typedef TheISA::MachInst MachInst;
 102     typedef TheISA::MiscReg MiscReg;
 103     typedef TheISA::FloatReg FloatReg;
 104     typedef TheISA::FloatRegBits FloatRegBits;
 105     typedef TheISA::CCReg CCReg;
 106     using VecRegContainer = TheISA::VecRegContainer;
 107     using VecElem = TheISA::VecElem;
 108   public:
 109     typedef ThreadContext::Status Status;
 110
 111   protected:
 112     union {
 113         FloatReg f[TheISA::NumFloatRegs];
 114         FloatRegBits i[TheISA::NumFloatRegs];
 115     } floatRegs;
 116     TheISA::IntReg intRegs[TheISA::NumIntRegs];
 117     VecRegContainer vecRegs[TheISA::NumVecRegs];
 118 #ifdef ISA_HAS_CC_REGS
 119     TheISA::CCReg ccRegs[TheISA::NumCCRegs];
 120 #endif
 121     TheISA::ISA *const isa;    // one "instance" of the current ISA.
 122
 123     TheISA::PCState _pcState;
 124
 125     /** Did this instruction execute or is it predicated false */
 126     bool predicate;
 127
 128   public:
 129     std::string name() const
 130     {
 131         return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
 132     }
 133
 134     ProxyThreadContext<SimpleThread> *tc;
 135
 136     System *system;
 137
 138     BaseTLB *itb;
 139     BaseTLB *dtb;
 140
 141     TheISA::Decoder decoder;
 142
 143     // constructor: initialize SimpleThread from given process structure
 144     // FS
 145     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
 146                  BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa,
 147                  bool use_kernel_stats = true);
 148     // SE
 149     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
 150                  Process *_process, BaseTLB *_itb, BaseTLB *_dtb,
 151                  TheISA::ISA *_isa);
 152
 153     virtual ~SimpleThread();
 154
 155     virtual void takeOverFrom(ThreadContext *oldContext);
 156
 157     void regStats(const std::string &name);
 158
 159     void copyState(ThreadContext *oldContext);
 160
 161     void serialize(CheckpointOut &cp) const override;
 162     void unserialize(CheckpointIn &cp) override;
 163     void startup();
 164
 165     /***************************************************************
 166      *  SimpleThread functions to provide CPU with access to various
 167      *  state.
 168      **************************************************************/
 169
 170     /** Returns the pointer to this SimpleThread's ThreadContext. Used
 171      *  when a ThreadContext must be passed to objects outside of the
 172      *  CPU.
 173      */
 174     ThreadContext *getTC() { return tc; }
 175
 176     void demapPage(Addr vaddr, uint64_t asn)
 177     {
 178         itb->demapPage(vaddr, asn);
 179         dtb->demapPage(vaddr, asn);
 180     }
 181
 182     void demapInstPage(Addr vaddr, uint64_t asn)
 183     {
 184         itb->demapPage(vaddr, asn);
 185     }
 186
 187     void demapDataPage(Addr vaddr, uint64_t asn)
 188     {
 189         dtb->demapPage(vaddr, asn);
 190     }
 191
 192     void dumpFuncProfile();
 193
 194     Fault hwrei();
 195
 196     bool simPalCheck(int palFunc);
 197
 198     /*******************************************
 199      * ThreadContext interface functions.
 200      ******************************************/
 201
 202     BaseCPU *getCpuPtr() { return baseCpu; }
 203
 204     BaseTLB *getITBPtr() { return itb; }
 205
 206     BaseTLB *getDTBPtr() { return dtb; }
 207
 208     CheckerCPU *getCheckerCpuPtr() { return NULL; }
 209
 210     TheISA::Decoder *getDecoderPtr() { return &decoder; }
 211
 212     System *getSystemPtr() { return system; }
 213
 214     Status status() const { return _status; }
 215
 216     void setStatus(Status newStatus) { _status = newStatus; }
 217
 218     /// Set the status to Active.
 219     void activate();
 220
 221     /// Set the status to Suspended.
 222     void suspend();
 223
 224     /// Set the status to Halted.
 225     void halt();
 226
 227     void copyArchRegs(ThreadContext *tc);
 228
 229     void clearArchRegs()
 230     {
 231         _pcState = 0;
 232         memset(intRegs, 0, sizeof(intRegs));
 233         memset(floatRegs.i, 0, sizeof(floatRegs.i));
 234         for (int i = 0; i < TheISA::NumVecRegs; i++) {
 235             vecRegs[i].zero();
 236         }
 237 #ifdef ISA_HAS_CC_REGS
 238         memset(ccRegs, 0, sizeof(ccRegs));
 239 #endif
 240         isa->clear();
 241     }
 242
 243     //
 244     // New accessors for new decoder.
 245     //
 246     uint64_t readIntReg(int reg_idx)
 247     {
 248         int flatIndex = isa->flattenIntIndex(reg_idx);
 249         assert(flatIndex < TheISA::NumIntRegs);
 250         uint64_t regVal(readIntRegFlat(flatIndex));
 251         DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
 252                 reg_idx, flatIndex, regVal);
 253         return regVal;
 254     }
 255
 256     FloatRegBits readFloatRegBits(int reg_idx)
 257     {
 258         int flatIndex = isa->flattenFloatIndex(reg_idx);
 259         assert(flatIndex < TheISA::NumFloatRegs);
 260         FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
 261         DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
 262                 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
 263         return regVal;
 264     }
 265
 266     const VecRegContainer&
 267     readVecReg(const RegId& reg) const
 268     {
 269         int flatIndex = isa->flattenVecIndex(reg.index());
 270         assert(flatIndex < TheISA::NumVecRegs);
 271         const VecRegContainer& regVal = readVecRegFlat(flatIndex);
 272         DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n",
 273                 reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print());
 274         return regVal;
 275     }
 276
 277     VecRegContainer&
 278     getWritableVecReg(const RegId& reg)
 279     {
 280         int flatIndex = isa->flattenVecIndex(reg.index());
 281         assert(flatIndex < TheISA::NumVecRegs);
 282         VecRegContainer& regVal = getWritableVecRegFlat(flatIndex);
 283         DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n",
 284                 reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print());
 285         return regVal;
 286     }
 287
 288     /** Vector Register Lane Interfaces. */
 289     /** @{ */
 290     /** Reads source vector <T> operand. */
 291     template <typename T>
 292     VecLaneT<T, true>
 293     readVecLane(const RegId& reg) const
 294     {
 295         int flatIndex = isa->flattenVecIndex(reg.index());
 296         assert(flatIndex < TheISA::NumVecRegs);
 297         auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex());
 298         DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n",
 299                 reg.index(), flatIndex, reg.elemIndex(), regVal);
 300         return regVal;
 301     }
 302
 303     /** Reads source vector 8bit operand. */
 304     virtual ConstVecLane8
 305     readVec8BitLaneReg(const RegId& reg) const
 306     { return readVecLane<uint8_t>(reg); }
 307
 308     /** Reads source vector 16bit operand. */
 309     virtual ConstVecLane16
 310     readVec16BitLaneReg(const RegId& reg) const
 311     { return readVecLane<uint16_t>(reg); }
 312
 313     /** Reads source vector 32bit operand. */
 314     virtual ConstVecLane32
 315     readVec32BitLaneReg(const RegId& reg) const
 316     { return readVecLane<uint32_t>(reg); }
 317
 318     /** Reads source vector 64bit operand. */
 319     virtual ConstVecLane64
 320     readVec64BitLaneReg(const RegId& reg) const
 321     { return readVecLane<uint64_t>(reg); }
 322
 323     /** Write a lane of the destination vector register. */
 324     template <typename LD>
 325     void setVecLaneT(const RegId& reg, const LD& val)
 326     {
 327         int flatIndex = isa->flattenVecIndex(reg.index());
 328         assert(flatIndex < TheISA::NumVecRegs);
 329         setVecLaneFlat(flatIndex, reg.elemIndex(), val);
 330         DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n",
 331                 reg.index(), flatIndex, reg.elemIndex(), val);
 332     }
 333     virtual void setVecLane(const RegId& reg,
 334             const LaneData<LaneSize::Byte>& val)
 335     { return setVecLaneT(reg, val); }
 336     virtual void setVecLane(const RegId& reg,
 337             const LaneData<LaneSize::TwoByte>& val)
 338     { return setVecLaneT(reg, val); }
 339     virtual void setVecLane(const RegId& reg,
 340             const LaneData<LaneSize::FourByte>& val)
 341     { return setVecLaneT(reg, val); }
 342     virtual void setVecLane(const RegId& reg,
 343             const LaneData<LaneSize::EightByte>& val)
 344     { return setVecLaneT(reg, val); }
 345     /** @} */
 346
 347     const VecElem& readVecElem(const RegId& reg) const
 348     {
 349         int flatIndex = isa->flattenVecElemIndex(reg.index());
 350         assert(flatIndex < TheISA::NumVecRegs);
 351         const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex());
 352         DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as"
 353                 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal);
 354         return regVal;
 355     }
 356
 357
 358     CCReg readCCReg(int reg_idx)
 359     {
 360 #ifdef ISA_HAS_CC_REGS
 361         int flatIndex = isa->flattenCCIndex(reg_idx);
 362         assert(0 <= flatIndex);
 363         assert(flatIndex < TheISA::NumCCRegs);
 364         uint64_t regVal(readCCRegFlat(flatIndex));
 365         DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
 366                 reg_idx, flatIndex, regVal);
 367         return regVal;
 368 #else
 369         panic("Tried to read a CC register.");
 370         return 0;
 371 #endif
 372     }
 373
 374     void setIntReg(int reg_idx, uint64_t val)
 375     {
 376         int flatIndex = isa->flattenIntIndex(reg_idx);
 377         assert(flatIndex < TheISA::NumIntRegs);
 378         DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
 379                 reg_idx, flatIndex, val);
 380         setIntRegFlat(flatIndex, val);
 381     }
 382
 383     void setFloatRegBits(int reg_idx, FloatRegBits val)
 384     {
 385         int flatIndex = isa->flattenFloatIndex(reg_idx);
 386         assert(flatIndex < TheISA::NumFloatRegs);
 387         // XXX: Fix array out of bounds compiler error for gem5.fast
 388         // when checkercpu enabled
 389         if (flatIndex < TheISA::NumFloatRegs)
 390             setFloatRegBitsFlat(flatIndex, val);
 391         DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
 392                 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
 393     }
 394
 395     void setVecReg(const RegId& reg, const VecRegContainer& val)
 396     {
 397         int flatIndex = isa->flattenVecIndex(reg.index());
 398         assert(flatIndex < TheISA::NumVecRegs);
 399         setVecRegFlat(flatIndex, val);
 400         DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n",
 401                 reg.index(), flatIndex, val.print());
 402     }
 403
 404     void setVecElem(const RegId& reg, const VecElem& val)
 405     {
 406         int flatIndex = isa->flattenVecElemIndex(reg.index());
 407         assert(flatIndex < TheISA::NumVecRegs);
 408         setVecElemFlat(flatIndex, reg.elemIndex(), val);
 409         DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to"
 410                 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val);
 411     }
 412
 413     void setCCReg(int reg_idx, CCReg val)
 414     {
 415 #ifdef ISA_HAS_CC_REGS
 416         int flatIndex = isa->flattenCCIndex(reg_idx);
 417         assert(flatIndex < TheISA::NumCCRegs);
 418         DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
 419                 reg_idx, flatIndex, val);
 420         setCCRegFlat(flatIndex, val);
 421 #else
 422         panic("Tried to set a CC register.");
 423 #endif
 424     }
 425
 426     TheISA::PCState
 427     pcState()
 428     {
 429         return _pcState;
 430     }
 431
 432     void
 433     pcState(const TheISA::PCState &val)
 434     {
 435         _pcState = val;
 436     }
 437
 438     void
 439     pcStateNoRecord(const TheISA::PCState &val)
 440     {
 441         _pcState = val;
 442     }
 443
 444     Addr
 445     instAddr()
 446     {
 447         return _pcState.instAddr();
 448     }
 449
 450     Addr
 451     nextInstAddr()
 452     {
 453         return _pcState.nextInstAddr();
 454     }
 455
 456     void
 457     setNPC(Addr val)
 458     {
 459         _pcState.setNPC(val);
 460     }
 461
 462     MicroPC
 463     microPC()
 464     {
 465         return _pcState.microPC();
 466     }
 467
 468     bool readPredicate()
 469     {
 470         return predicate;
 471     }
 472
 473     void setPredicate(bool val)
 474     {
 475         predicate = val;
 476     }
 477
 478     MiscReg
 479     readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
 480     {
 481         return isa->readMiscRegNoEffect(misc_reg);
 482     }
 483
 484     MiscReg
 485     readMiscReg(int misc_reg, ThreadID tid = 0)
 486     {
 487         return isa->readMiscReg(misc_reg, tc);
 488     }
 489
 490     void
 491     setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
 492     {
 493         return isa->setMiscRegNoEffect(misc_reg, val);
 494     }
 495
 496     void
 497     setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
 498     {
 499         return isa->setMiscReg(misc_reg, val, tc);
 500     }
 501
 502     RegId
 503     flattenRegId(const RegId& regId) const
 504     {
 505         return isa->flattenRegId(regId);
 506     }
 507
 508     unsigned readStCondFailures() { return storeCondFailures; }
 509
 510     void setStCondFailures(unsigned sc_failures)
 511     { storeCondFailures = sc_failures; }
 512
 513     void syscall(int64_t callnum, Fault *fault)
 514     {
 515         process->syscall(callnum, tc, fault);
 516     }
 517
 518     uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
 519     void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
 520
 521     FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
 522     void setFloatRegBitsFlat(int idx, FloatRegBits val) {
 523         floatRegs.i[idx] = val;
 524     }
 525
 526     const VecRegContainer& readVecRegFlat(const RegIndex& reg) const
 527     {
 528         return vecRegs[reg];
 529     }
 530
 531     VecRegContainer& getWritableVecRegFlat(const RegIndex& reg)
 532     {
 533         return vecRegs[reg];
 534     }
 535
 536     void setVecRegFlat(const RegIndex& reg, const VecRegContainer& val)
 537     {
 538         vecRegs[reg] = val;
 539     }
 540
 541     template <typename T>
 542     VecLaneT<T, true> readVecLaneFlat(const RegIndex& reg, int lId) const
 543     {
 544         return vecRegs[reg].laneView<T>(lId);
 545     }
 546
 547     template <typename LD>
 548     void setVecLaneFlat(const RegIndex& reg, int lId, const LD& val)
 549     {
 550         vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
 551     }
 552
 553     const VecElem& readVecElemFlat(const RegIndex& reg,
 554                                    const ElemIndex& elemIndex) const
 555     {
 556         return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
 557     }
 558
 559     void setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex,
 560                         const VecElem val)
 561     {
 562         vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
 563     }
 564
 565 #ifdef ISA_HAS_CC_REGS
 566     CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
 567     void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
 568 #else
 569     CCReg readCCRegFlat(int idx)
 570     { panic("readCCRegFlat w/no CC regs!\n"); }
 571
 572     void setCCRegFlat(int idx, CCReg val)
 573     { panic("setCCRegFlat w/no CC regs!\n"); }
 574 #endif
 575 };
 576
 577
 578 #endif // __CPU_CPU_EXEC_CONTEXT_HH__