src/cpu/simple_thread.hh

   1 /*
   2  * Copyright (c) 2001-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #ifndef __CPU_SIMPLE_THREAD_HH__
  33 #define __CPU_SIMPLE_THREAD_HH__
  34
  35 #include "arch/isa.hh"
  36 #include "arch/isa_traits.hh"
  37 #include "arch/registers.hh"
  38 #include "arch/tlb.hh"
  39 #include "arch/types.hh"
  40 #include "base/types.hh"
  41 #include "config/full_system.hh"
  42 #include "cpu/thread_context.hh"
  43 #include "cpu/thread_state.hh"
  44 #include "mem/request.hh"
  45 #include "sim/byteswap.hh"
  46 #include "sim/eventq.hh"
  47 #include "sim/serialize.hh"
  48
  49 class BaseCPU;
  50
  51 #if FULL_SYSTEM
  52
  53 #include "sim/system.hh"
  54
  55 class FunctionProfile;
  56 class ProfileNode;
  57 class FunctionalPort;
  58 class PhysicalPort;
  59
  60 namespace TheISA {
  61     namespace Kernel {
  62         class Statistics;
  63     };
  64 };
  65
  66 #else // !FULL_SYSTEM
  67
  68 #include "sim/process.hh"
  69 #include "mem/page_table.hh"
  70 class TranslatingPort;
  71
  72 #endif // FULL_SYSTEM
  73
  74 /**
  75  * The SimpleThread object provides a combination of the ThreadState
  76  * object and the ThreadContext interface. It implements the
  77  * ThreadContext interface so that a ProxyThreadContext class can be
  78  * made using SimpleThread as the template parameter (see
  79  * thread_context.hh). It adds to the ThreadState object by adding all
  80  * the objects needed for simple functional execution, including a
  81  * simple architectural register file, and pointers to the ITB and DTB
  82  * in full system mode. For CPU models that do not need more advanced
  83  * ways to hold state (i.e. a separate physical register file, or
  84  * separate fetch and commit PC's), this SimpleThread class provides
  85  * all the necessary state for full architecture-level functional
  86  * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
  87  * examples.
  88  */
  89
  90 class SimpleThread : public ThreadState
  91 {
  92   protected:
  93     typedef TheISA::MachInst MachInst;
  94     typedef TheISA::MiscReg MiscReg;
  95     typedef TheISA::FloatReg FloatReg;
  96     typedef TheISA::FloatRegBits FloatRegBits;
  97   public:
  98     typedef ThreadContext::Status Status;
  99
 100   protected:
 101     union {
 102         FloatReg f[TheISA::NumFloatRegs];
 103         FloatRegBits i[TheISA::NumFloatRegs];
 104     } floatRegs;
 105     TheISA::IntReg intRegs[TheISA::NumIntRegs];
 106     TheISA::ISA isa;    // one "instance" of the current ISA.
 107
 108     /** The current microcode pc for the currently executing macro
 109      * operation.
 110      */
 111     MicroPC microPC;
 112
 113     /** The next microcode pc for the currently executing macro
 114      * operation.
 115      */
 116     MicroPC nextMicroPC;
 117
 118     /** The current pc.
 119      */
 120     Addr PC;
 121
 122     /** The next pc.
 123      */
 124     Addr nextPC;
 125
 126     /** The next next pc.
 127      */
 128     Addr nextNPC;
 129
 130   public:
 131     // pointer to CPU associated with this SimpleThread
 132     BaseCPU *cpu;
 133
 134     ProxyThreadContext<SimpleThread> *tc;
 135
 136     System *system;
 137
 138     TheISA::TLB *itb;
 139     TheISA::TLB *dtb;
 140
 141     // constructor: initialize SimpleThread from given process structure
 142 #if FULL_SYSTEM
 143     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
 144                  TheISA::TLB *_itb, TheISA::TLB *_dtb,
 145                  bool use_kernel_stats = true);
 146 #else
 147     SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
 148                  TheISA::TLB *_itb, TheISA::TLB *_dtb);
 149 #endif
 150
 151     SimpleThread();
 152
 153     virtual ~SimpleThread();
 154
 155     virtual void takeOverFrom(ThreadContext *oldContext);
 156
 157     void regStats(const std::string &name);
 158
 159     void copyTC(ThreadContext *context);
 160
 161     void copyState(ThreadContext *oldContext);
 162
 163     void serialize(std::ostream &os);
 164     void unserialize(Checkpoint *cp, const std::string &section);
 165
 166     /***************************************************************
 167      *  SimpleThread functions to provide CPU with access to various
 168      *  state.
 169      **************************************************************/
 170
 171     /** Returns the pointer to this SimpleThread's ThreadContext. Used
 172      *  when a ThreadContext must be passed to objects outside of the
 173      *  CPU.
 174      */
 175     ThreadContext *getTC() { return tc; }
 176
 177     void demapPage(Addr vaddr, uint64_t asn)
 178     {
 179         itb->demapPage(vaddr, asn);
 180         dtb->demapPage(vaddr, asn);
 181     }
 182
 183     void demapInstPage(Addr vaddr, uint64_t asn)
 184     {
 185         itb->demapPage(vaddr, asn);
 186     }
 187
 188     void demapDataPage(Addr vaddr, uint64_t asn)
 189     {
 190         dtb->demapPage(vaddr, asn);
 191     }
 192
 193 #if FULL_SYSTEM
 194     void dumpFuncProfile();
 195
 196     Fault hwrei();
 197
 198     bool simPalCheck(int palFunc);
 199
 200 #endif
 201
 202     /*******************************************
 203      * ThreadContext interface functions.
 204      ******************************************/
 205
 206     BaseCPU *getCpuPtr() { return cpu; }
 207
 208     TheISA::TLB *getITBPtr() { return itb; }
 209
 210     TheISA::TLB *getDTBPtr() { return dtb; }
 211
 212     System *getSystemPtr() { return system; }
 213
 214 #if FULL_SYSTEM
 215     FunctionalPort *getPhysPort() { return physPort; }
 216
 217     /** Return a virtual port. This port cannot be cached locally in an object.
 218      * After a CPU switch it may point to the wrong memory object which could
 219      * mean stale data.
 220      */
 221     VirtualPort *getVirtPort() { return virtPort; }
 222 #endif
 223
 224     Status status() const { return _status; }
 225
 226     void setStatus(Status newStatus) { _status = newStatus; }
 227
 228     /// Set the status to Active.  Optional delay indicates number of
 229     /// cycles to wait before beginning execution.
 230     void activate(int delay = 1);
 231
 232     /// Set the status to Suspended.
 233     void suspend();
 234
 235     /// Set the status to Halted.
 236     void halt();
 237
 238     virtual bool misspeculating();
 239
 240     Fault instRead(RequestPtr &req)
 241     {
 242         panic("instRead not implemented");
 243         // return funcPhysMem->read(req, inst);
 244         return NoFault;
 245     }
 246
 247     void copyArchRegs(ThreadContext *tc);
 248
 249     void clearArchRegs()
 250     {
 251         microPC = 0;
 252         nextMicroPC = 1;
 253         PC = nextPC = nextNPC = 0;
 254         memset(intRegs, 0, sizeof(intRegs));
 255         memset(floatRegs.i, 0, sizeof(floatRegs.i));
 256     }
 257
 258     //
 259     // New accessors for new decoder.
 260     //
 261     uint64_t readIntReg(int reg_idx)
 262     {
 263         int flatIndex = isa.flattenIntIndex(reg_idx);
 264         assert(flatIndex < TheISA::NumIntRegs);
 265         uint64_t regVal = intRegs[flatIndex];
 266         DPRINTF(IntRegs, "Reading int reg %d as %#x.\n", reg_idx, regVal);
 267         return regVal;
 268     }
 269
 270     FloatReg readFloatReg(int reg_idx)
 271     {
 272         int flatIndex = isa.flattenFloatIndex(reg_idx);
 273         assert(flatIndex < TheISA::NumFloatRegs);
 274         return floatRegs.f[flatIndex];
 275     }
 276
 277     FloatRegBits readFloatRegBits(int reg_idx)
 278     {
 279         int flatIndex = isa.flattenFloatIndex(reg_idx);
 280         assert(flatIndex < TheISA::NumFloatRegs);
 281         return floatRegs.i[flatIndex];
 282     }
 283
 284     void setIntReg(int reg_idx, uint64_t val)
 285     {
 286         int flatIndex = isa.flattenIntIndex(reg_idx);
 287         assert(flatIndex < TheISA::NumIntRegs);
 288         DPRINTF(IntRegs, "Setting int reg %d to %#x.\n", reg_idx, val);
 289         intRegs[flatIndex] = val;
 290     }
 291
 292     void setFloatReg(int reg_idx, FloatReg val)
 293     {
 294         int flatIndex = isa.flattenFloatIndex(reg_idx);
 295         assert(flatIndex < TheISA::NumFloatRegs);
 296         floatRegs.f[flatIndex] = val;
 297     }
 298
 299     void setFloatRegBits(int reg_idx, FloatRegBits val)
 300     {
 301         int flatIndex = isa.flattenFloatIndex(reg_idx);
 302         assert(flatIndex < TheISA::NumFloatRegs);
 303         floatRegs.i[flatIndex] = val;
 304     }
 305
 306     uint64_t readPC()
 307     {
 308         return PC;
 309     }
 310
 311     void setPC(uint64_t val)
 312     {
 313         PC = val;
 314     }
 315
 316     uint64_t readMicroPC()
 317     {
 318         return microPC;
 319     }
 320
 321     void setMicroPC(uint64_t val)
 322     {
 323         microPC = val;
 324     }
 325
 326     uint64_t readNextPC()
 327     {
 328         return nextPC;
 329     }
 330
 331     void setNextPC(uint64_t val)
 332     {
 333         nextPC = val;
 334     }
 335
 336     uint64_t readNextMicroPC()
 337     {
 338         return nextMicroPC;
 339     }
 340
 341     void setNextMicroPC(uint64_t val)
 342     {
 343         nextMicroPC = val;
 344     }
 345
 346     uint64_t readNextNPC()
 347     {
 348 #if ISA_HAS_DELAY_SLOT
 349         return nextNPC;
 350 #else
 351         return nextPC + sizeof(TheISA::MachInst);
 352 #endif
 353     }
 354
 355     void setNextNPC(uint64_t val)
 356     {
 357 #if ISA_HAS_DELAY_SLOT
 358         nextNPC = val;
 359 #endif
 360     }
 361
 362     MiscReg
 363     readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
 364     {
 365         return isa.readMiscRegNoEffect(misc_reg);
 366     }
 367
 368     MiscReg
 369     readMiscReg(int misc_reg, ThreadID tid = 0)
 370     {
 371         return isa.readMiscReg(misc_reg, tc);
 372     }
 373
 374     void
 375     setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
 376     {
 377         return isa.setMiscRegNoEffect(misc_reg, val);
 378     }
 379
 380     void
 381     setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
 382     {
 383         return isa.setMiscReg(misc_reg, val, tc);
 384     }
 385
 386     int
 387     flattenIntIndex(int reg)
 388     {
 389         return isa.flattenIntIndex(reg);
 390     }
 391
 392     int
 393     flattenFloatIndex(int reg)
 394     {
 395         return isa.flattenFloatIndex(reg);
 396     }
 397
 398     unsigned readStCondFailures() { return storeCondFailures; }
 399
 400     void setStCondFailures(unsigned sc_failures)
 401     { storeCondFailures = sc_failures; }
 402
 403 #if !FULL_SYSTEM
 404     void syscall(int64_t callnum)
 405     {
 406         process->syscall(callnum, tc);
 407     }
 408 #endif
 409 };
 410
 411
 412 // for non-speculative execution context, spec_mode is always false
 413 inline bool
 414 SimpleThread::misspeculating()
 415 {
 416     return false;
 417 }
 418
 419 #endif // __CPU_CPU_EXEC_CONTEXT_HH__