src/cpu/simple_thread.hh

   1 /*
   2  * Copyright (c) 2001-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #ifndef __CPU_SIMPLE_THREAD_HH__
  33 #define __CPU_SIMPLE_THREAD_HH__
  34
  35 #include "arch/isa.hh"
  36 #include "arch/isa_traits.hh"
  37 #include "arch/registers.hh"
  38 #include "arch/tlb.hh"
  39 #include "arch/types.hh"
  40 #include "base/types.hh"
  41 #include "config/full_system.hh"
  42 #include "config/the_isa.hh"
  43 #include "cpu/thread_context.hh"
  44 #include "cpu/thread_state.hh"
  45 #include "debug/FloatRegs.hh"
  46 #include "debug/IntRegs.hh"
  47 #include "mem/request.hh"
  48 #include "sim/byteswap.hh"
  49 #include "sim/eventq.hh"
  50 #include "sim/serialize.hh"
  51
  52 class BaseCPU;
  53
  54 #if FULL_SYSTEM
  55
  56 #include "sim/system.hh"
  57
  58 class FunctionProfile;
  59 class ProfileNode;
  60 class FunctionalPort;
  61 class PhysicalPort;
  62
  63 namespace TheISA {
  64     namespace Kernel {
  65         class Statistics;
  66     };
  67 };
  68
  69 #else // !FULL_SYSTEM
  70
  71 #include "mem/page_table.hh"
  72 #include "sim/process.hh"
  73 class TranslatingPort;
  74
  75 #endif // FULL_SYSTEM
  76
  77 /**
  78  * The SimpleThread object provides a combination of the ThreadState
  79  * object and the ThreadContext interface. It implements the
  80  * ThreadContext interface so that a ProxyThreadContext class can be
  81  * made using SimpleThread as the template parameter (see
  82  * thread_context.hh). It adds to the ThreadState object by adding all
  83  * the objects needed for simple functional execution, including a
  84  * simple architectural register file, and pointers to the ITB and DTB
  85  * in full system mode. For CPU models that do not need more advanced
  86  * ways to hold state (i.e. a separate physical register file, or
  87  * separate fetch and commit PC's), this SimpleThread class provides
  88  * all the necessary state for full architecture-level functional
  89  * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
  90  * examples.
  91  */
  92
  93 class SimpleThread : public ThreadState
  94 {
  95   protected:
  96     typedef TheISA::MachInst MachInst;
  97     typedef TheISA::MiscReg MiscReg;
  98     typedef TheISA::FloatReg FloatReg;
  99     typedef TheISA::FloatRegBits FloatRegBits;
 100   public:
 101     typedef ThreadContext::Status Status;
 102
 103   protected:
 104     union {
 105         FloatReg f[TheISA::NumFloatRegs];
 106         FloatRegBits i[TheISA::NumFloatRegs];
 107     } floatRegs;
 108     TheISA::IntReg intRegs[TheISA::NumIntRegs];
 109     TheISA::ISA isa;    // one "instance" of the current ISA.
 110
 111     TheISA::PCState _pcState;
 112
 113     /** Did this instruction execute or is it predicated false */
 114     bool predicate;
 115
 116   public:
 117     std::string name() const
 118     {
 119         return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId());
 120     }
 121
 122     // pointer to CPU associated with this SimpleThread
 123     BaseCPU *cpu;
 124
 125     ProxyThreadContext<SimpleThread> *tc;
 126
 127     System *system;
 128
 129     TheISA::TLB *itb;
 130     TheISA::TLB *dtb;
 131
 132     // constructor: initialize SimpleThread from given process structure
 133 #if FULL_SYSTEM
 134     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
 135                  TheISA::TLB *_itb, TheISA::TLB *_dtb,
 136                  bool use_kernel_stats = true);
 137 #else
 138     SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
 139                  TheISA::TLB *_itb, TheISA::TLB *_dtb);
 140 #endif
 141
 142     SimpleThread();
 143
 144     virtual ~SimpleThread();
 145
 146     virtual void takeOverFrom(ThreadContext *oldContext);
 147
 148     void regStats(const std::string &name);
 149
 150     void copyTC(ThreadContext *context);
 151
 152     void copyState(ThreadContext *oldContext);
 153
 154     void serialize(std::ostream &os);
 155     void unserialize(Checkpoint *cp, const std::string &section);
 156
 157     /***************************************************************
 158      *  SimpleThread functions to provide CPU with access to various
 159      *  state.
 160      **************************************************************/
 161
 162     /** Returns the pointer to this SimpleThread's ThreadContext. Used
 163      *  when a ThreadContext must be passed to objects outside of the
 164      *  CPU.
 165      */
 166     ThreadContext *getTC() { return tc; }
 167
 168     void demapPage(Addr vaddr, uint64_t asn)
 169     {
 170         itb->demapPage(vaddr, asn);
 171         dtb->demapPage(vaddr, asn);
 172     }
 173
 174     void demapInstPage(Addr vaddr, uint64_t asn)
 175     {
 176         itb->demapPage(vaddr, asn);
 177     }
 178
 179     void demapDataPage(Addr vaddr, uint64_t asn)
 180     {
 181         dtb->demapPage(vaddr, asn);
 182     }
 183
 184 #if FULL_SYSTEM
 185     void dumpFuncProfile();
 186
 187     Fault hwrei();
 188
 189     bool simPalCheck(int palFunc);
 190
 191 #endif
 192
 193     /*******************************************
 194      * ThreadContext interface functions.
 195      ******************************************/
 196
 197     BaseCPU *getCpuPtr() { return cpu; }
 198
 199     TheISA::TLB *getITBPtr() { return itb; }
 200
 201     TheISA::TLB *getDTBPtr() { return dtb; }
 202
 203     System *getSystemPtr() { return system; }
 204
 205 #if FULL_SYSTEM
 206     FunctionalPort *getPhysPort() { return physPort; }
 207
 208     /** Return a virtual port. This port cannot be cached locally in an object.
 209      * After a CPU switch it may point to the wrong memory object which could
 210      * mean stale data.
 211      */
 212     VirtualPort *getVirtPort() { return virtPort; }
 213 #endif
 214
 215     Status status() const { return _status; }
 216
 217     void setStatus(Status newStatus) { _status = newStatus; }
 218
 219     /// Set the status to Active.  Optional delay indicates number of
 220     /// cycles to wait before beginning execution.
 221     void activate(int delay = 1);
 222
 223     /// Set the status to Suspended.
 224     void suspend();
 225
 226     /// Set the status to Halted.
 227     void halt();
 228
 229     virtual bool misspeculating();
 230
 231     void copyArchRegs(ThreadContext *tc);
 232
 233     void clearArchRegs()
 234     {
 235         _pcState = 0;
 236         memset(intRegs, 0, sizeof(intRegs));
 237         memset(floatRegs.i, 0, sizeof(floatRegs.i));
 238         isa.clear();
 239     }
 240
 241     //
 242     // New accessors for new decoder.
 243     //
 244     uint64_t readIntReg(int reg_idx)
 245     {
 246         int flatIndex = isa.flattenIntIndex(reg_idx);
 247         assert(flatIndex < TheISA::NumIntRegs);
 248         uint64_t regVal = intRegs[flatIndex];
 249         DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
 250                 reg_idx, flatIndex, regVal);
 251         return regVal;
 252     }
 253
 254     FloatReg readFloatReg(int reg_idx)
 255     {
 256         int flatIndex = isa.flattenFloatIndex(reg_idx);
 257         assert(flatIndex < TheISA::NumFloatRegs);
 258         FloatReg regVal = floatRegs.f[flatIndex];
 259         DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
 260                 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
 261         return regVal;
 262     }
 263
 264     FloatRegBits readFloatRegBits(int reg_idx)
 265     {
 266         int flatIndex = isa.flattenFloatIndex(reg_idx);
 267         assert(flatIndex < TheISA::NumFloatRegs);
 268         FloatRegBits regVal = floatRegs.i[flatIndex];
 269         DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
 270                 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
 271         return regVal;
 272     }
 273
 274     void setIntReg(int reg_idx, uint64_t val)
 275     {
 276         int flatIndex = isa.flattenIntIndex(reg_idx);
 277         assert(flatIndex < TheISA::NumIntRegs);
 278         DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
 279                 reg_idx, flatIndex, val);
 280         intRegs[flatIndex] = val;
 281     }
 282
 283     void setFloatReg(int reg_idx, FloatReg val)
 284     {
 285         int flatIndex = isa.flattenFloatIndex(reg_idx);
 286         assert(flatIndex < TheISA::NumFloatRegs);
 287         floatRegs.f[flatIndex] = val;
 288         DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
 289                 reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
 290     }
 291
 292     void setFloatRegBits(int reg_idx, FloatRegBits val)
 293     {
 294         int flatIndex = isa.flattenFloatIndex(reg_idx);
 295         assert(flatIndex < TheISA::NumFloatRegs);
 296         floatRegs.i[flatIndex] = val;
 297         DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
 298                 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
 299     }
 300
 301     TheISA::PCState
 302     pcState()
 303     {
 304         return _pcState;
 305     }
 306
 307     void
 308     pcState(const TheISA::PCState &val)
 309     {
 310         _pcState = val;
 311     }
 312
 313     Addr
 314     instAddr()
 315     {
 316         return _pcState.instAddr();
 317     }
 318
 319     Addr
 320     nextInstAddr()
 321     {
 322         return _pcState.nextInstAddr();
 323     }
 324
 325     MicroPC
 326     microPC()
 327     {
 328         return _pcState.microPC();
 329     }
 330
 331     bool readPredicate()
 332     {
 333         return predicate;
 334     }
 335
 336     void setPredicate(bool val)
 337     {
 338         predicate = val;
 339     }
 340
 341     MiscReg
 342     readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
 343     {
 344         return isa.readMiscRegNoEffect(misc_reg);
 345     }
 346
 347     MiscReg
 348     readMiscReg(int misc_reg, ThreadID tid = 0)
 349     {
 350         return isa.readMiscReg(misc_reg, tc);
 351     }
 352
 353     void
 354     setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
 355     {
 356         return isa.setMiscRegNoEffect(misc_reg, val);
 357     }
 358
 359     void
 360     setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
 361     {
 362         return isa.setMiscReg(misc_reg, val, tc);
 363     }
 364
 365     int
 366     flattenIntIndex(int reg)
 367     {
 368         return isa.flattenIntIndex(reg);
 369     }
 370
 371     int
 372     flattenFloatIndex(int reg)
 373     {
 374         return isa.flattenFloatIndex(reg);
 375     }
 376
 377     unsigned readStCondFailures() { return storeCondFailures; }
 378
 379     void setStCondFailures(unsigned sc_failures)
 380     { storeCondFailures = sc_failures; }
 381
 382 #if !FULL_SYSTEM
 383     void syscall(int64_t callnum)
 384     {
 385         process->syscall(callnum, tc);
 386     }
 387 #endif
 388 };
 389
 390
 391 // for non-speculative execution context, spec_mode is always false
 392 inline bool
 393 SimpleThread::misspeculating()
 394 {
 395     return false;
 396 }
 397
 398 #endif // __CPU_CPU_EXEC_CONTEXT_HH__