2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #ifndef __CPU_SIMPLE_THREAD_HH__
33 #define __CPU_SIMPLE_THREAD_HH__
35 #include "arch/isa.hh"
36 #include "arch/isa_traits.hh"
37 #include "arch/registers.hh"
38 #include "arch/tlb.hh"
39 #include "arch/types.hh"
40 #include "base/types.hh"
41 #include "config/full_system.hh"
42 #include "config/the_isa.hh"
43 #include "cpu/thread_context.hh"
44 #include "cpu/thread_state.hh"
45 #include "debug/FloatRegs.hh"
46 #include "debug/IntRegs.hh"
47 #include "mem/request.hh"
48 #include "sim/byteswap.hh"
49 #include "sim/eventq.hh"
50 #include "sim/serialize.hh"
56 #include "sim/system.hh"
58 class FunctionProfile;
71 #include "mem/page_table.hh"
72 #include "sim/process.hh"
73 class TranslatingPort;
78 * The SimpleThread object provides a combination of the ThreadState
79 * object and the ThreadContext interface. It implements the
80 * ThreadContext interface so that a ProxyThreadContext class can be
81 * made using SimpleThread as the template parameter (see
82 * thread_context.hh). It adds to the ThreadState object by adding all
83 * the objects needed for simple functional execution, including a
84 * simple architectural register file, and pointers to the ITB and DTB
85 * in full system mode. For CPU models that do not need more advanced
86 * ways to hold state (i.e. a separate physical register file, or
87 * separate fetch and commit PC's), this SimpleThread class provides
88 * all the necessary state for full architecture-level functional
89 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
93 class SimpleThread : public ThreadState
96 typedef TheISA::MachInst MachInst;
97 typedef TheISA::MiscReg MiscReg;
98 typedef TheISA::FloatReg FloatReg;
99 typedef TheISA::FloatRegBits FloatRegBits;
101 typedef ThreadContext::Status Status;
105 FloatReg f[TheISA::NumFloatRegs];
106 FloatRegBits i[TheISA::NumFloatRegs];
108 TheISA::IntReg intRegs[TheISA::NumIntRegs];
109 TheISA::ISA isa; // one "instance" of the current ISA.
111 TheISA::PCState _pcState;
113 /** Did this instruction execute or is it predicated false */
117 std::string name() const
119 return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId());
122 // pointer to CPU associated with this SimpleThread
125 ProxyThreadContext<SimpleThread> *tc;
132 // constructor: initialize SimpleThread from given process structure
134 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
135 TheISA::TLB *_itb, TheISA::TLB *_dtb,
136 bool use_kernel_stats = true);
138 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
139 TheISA::TLB *_itb, TheISA::TLB *_dtb);
144 virtual ~SimpleThread();
146 virtual void takeOverFrom(ThreadContext *oldContext);
148 void regStats(const std::string &name);
150 void copyTC(ThreadContext *context);
152 void copyState(ThreadContext *oldContext);
154 void serialize(std::ostream &os);
155 void unserialize(Checkpoint *cp, const std::string §ion);
157 /***************************************************************
158 * SimpleThread functions to provide CPU with access to various
160 **************************************************************/
162 /** Returns the pointer to this SimpleThread's ThreadContext. Used
163 * when a ThreadContext must be passed to objects outside of the
166 ThreadContext *getTC() { return tc; }
168 void demapPage(Addr vaddr, uint64_t asn)
170 itb->demapPage(vaddr, asn);
171 dtb->demapPage(vaddr, asn);
174 void demapInstPage(Addr vaddr, uint64_t asn)
176 itb->demapPage(vaddr, asn);
179 void demapDataPage(Addr vaddr, uint64_t asn)
181 dtb->demapPage(vaddr, asn);
185 void dumpFuncProfile();
189 bool simPalCheck(int palFunc);
193 /*******************************************
194 * ThreadContext interface functions.
195 ******************************************/
197 BaseCPU *getCpuPtr() { return cpu; }
199 TheISA::TLB *getITBPtr() { return itb; }
201 TheISA::TLB *getDTBPtr() { return dtb; }
203 System *getSystemPtr() { return system; }
206 FunctionalPort *getPhysPort() { return physPort; }
208 /** Return a virtual port. This port cannot be cached locally in an object.
209 * After a CPU switch it may point to the wrong memory object which could
212 VirtualPort *getVirtPort() { return virtPort; }
215 Status status() const { return _status; }
217 void setStatus(Status newStatus) { _status = newStatus; }
219 /// Set the status to Active. Optional delay indicates number of
220 /// cycles to wait before beginning execution.
221 void activate(int delay = 1);
223 /// Set the status to Suspended.
226 /// Set the status to Halted.
229 virtual bool misspeculating();
231 void copyArchRegs(ThreadContext *tc);
236 memset(intRegs, 0, sizeof(intRegs));
237 memset(floatRegs.i, 0, sizeof(floatRegs.i));
242 // New accessors for new decoder.
244 uint64_t readIntReg(int reg_idx)
246 int flatIndex = isa.flattenIntIndex(reg_idx);
247 assert(flatIndex < TheISA::NumIntRegs);
248 uint64_t regVal = intRegs[flatIndex];
249 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
250 reg_idx, flatIndex, regVal);
254 FloatReg readFloatReg(int reg_idx)
256 int flatIndex = isa.flattenFloatIndex(reg_idx);
257 assert(flatIndex < TheISA::NumFloatRegs);
258 FloatReg regVal = floatRegs.f[flatIndex];
259 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
260 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
264 FloatRegBits readFloatRegBits(int reg_idx)
266 int flatIndex = isa.flattenFloatIndex(reg_idx);
267 assert(flatIndex < TheISA::NumFloatRegs);
268 FloatRegBits regVal = floatRegs.i[flatIndex];
269 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
270 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
274 void setIntReg(int reg_idx, uint64_t val)
276 int flatIndex = isa.flattenIntIndex(reg_idx);
277 assert(flatIndex < TheISA::NumIntRegs);
278 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
279 reg_idx, flatIndex, val);
280 intRegs[flatIndex] = val;
283 void setFloatReg(int reg_idx, FloatReg val)
285 int flatIndex = isa.flattenFloatIndex(reg_idx);
286 assert(flatIndex < TheISA::NumFloatRegs);
287 floatRegs.f[flatIndex] = val;
288 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
289 reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
292 void setFloatRegBits(int reg_idx, FloatRegBits val)
294 int flatIndex = isa.flattenFloatIndex(reg_idx);
295 assert(flatIndex < TheISA::NumFloatRegs);
296 floatRegs.i[flatIndex] = val;
297 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
298 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
308 pcState(const TheISA::PCState &val)
316 return _pcState.instAddr();
322 return _pcState.nextInstAddr();
328 return _pcState.microPC();
336 void setPredicate(bool val)
342 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
344 return isa.readMiscRegNoEffect(misc_reg);
348 readMiscReg(int misc_reg, ThreadID tid = 0)
350 return isa.readMiscReg(misc_reg, tc);
354 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
356 return isa.setMiscRegNoEffect(misc_reg, val);
360 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
362 return isa.setMiscReg(misc_reg, val, tc);
366 flattenIntIndex(int reg)
368 return isa.flattenIntIndex(reg);
372 flattenFloatIndex(int reg)
374 return isa.flattenFloatIndex(reg);
377 unsigned readStCondFailures() { return storeCondFailures; }
379 void setStCondFailures(unsigned sc_failures)
380 { storeCondFailures = sc_failures; }
383 void syscall(int64_t callnum)
385 process->syscall(callnum, tc);
391 // for non-speculative execution context, spec_mode is always false
393 SimpleThread::misspeculating()
398 #endif // __CPU_CPU_EXEC_CONTEXT_HH__