src/cpu/simple_thread.hh

   1 /*
   2  * Copyright (c) 2001-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #ifndef __CPU_SIMPLE_THREAD_HH__
  33 #define __CPU_SIMPLE_THREAD_HH__
  34
  35 #include "arch/isa_traits.hh"
  36 #include "arch/regfile.hh"
  37 #include "arch/syscallreturn.hh"
  38 #include "config/full_system.hh"
  39 #include "cpu/thread_context.hh"
  40 #include "cpu/thread_state.hh"
  41 #include "mem/physical.hh"
  42 #include "mem/request.hh"
  43 #include "sim/byteswap.hh"
  44 #include "sim/eventq.hh"
  45 #include "sim/host.hh"
  46 #include "sim/serialize.hh"
  47
  48 class BaseCPU;
  49
  50 #if FULL_SYSTEM
  51
  52 #include "sim/system.hh"
  53 #include "arch/tlb.hh"
  54
  55 class FunctionProfile;
  56 class ProfileNode;
  57 class FunctionalPort;
  58 class PhysicalPort;
  59
  60 namespace TheISA {
  61     namespace Kernel {
  62         class Statistics;
  63     };
  64 };
  65
  66 #else // !FULL_SYSTEM
  67
  68 #include "sim/process.hh"
  69 #include "mem/page_table.hh"
  70 class TranslatingPort;
  71
  72 #endif // FULL_SYSTEM
  73
  74 /**
  75  * The SimpleThread object provides a combination of the ThreadState
  76  * object and the ThreadContext interface. It implements the
  77  * ThreadContext interface so that a ProxyThreadContext class can be
  78  * made using SimpleThread as the template parameter (see
  79  * thread_context.hh). It adds to the ThreadState object by adding all
  80  * the objects needed for simple functional execution, including a
  81  * simple architectural register file, and pointers to the ITB and DTB
  82  * in full system mode. For CPU models that do not need more advanced
  83  * ways to hold state (i.e. a separate physical register file, or
  84  * separate fetch and commit PC's), this SimpleThread class provides
  85  * all the necessary state for full architecture-level functional
  86  * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
  87  * examples.
  88  */
  89
  90 class SimpleThread : public ThreadState
  91 {
  92   protected:
  93     typedef TheISA::RegFile RegFile;
  94     typedef TheISA::MachInst MachInst;
  95     typedef TheISA::MiscRegFile MiscRegFile;
  96     typedef TheISA::MiscReg MiscReg;
  97     typedef TheISA::FloatReg FloatReg;
  98     typedef TheISA::FloatRegBits FloatRegBits;
  99   public:
 100     typedef ThreadContext::Status Status;
 101
 102   protected:
 103     RegFile regs;       // correct-path register context
 104
 105   public:
 106     // pointer to CPU associated with this SimpleThread
 107     BaseCPU *cpu;
 108
 109     ProxyThreadContext<SimpleThread> *tc;
 110
 111     System *system;
 112
 113 #if FULL_SYSTEM
 114     TheISA::ITB *itb;
 115     TheISA::DTB *dtb;
 116 #endif
 117
 118     // constructor: initialize SimpleThread from given process structure
 119 #if FULL_SYSTEM
 120     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
 121                  TheISA::ITB *_itb, TheISA::DTB *_dtb,
 122                  bool use_kernel_stats = true);
 123 #else
 124     SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
 125 #endif
 126
 127     SimpleThread();
 128
 129     virtual ~SimpleThread();
 130
 131     virtual void takeOverFrom(ThreadContext *oldContext);
 132
 133     void regStats(const std::string &name);
 134
 135     void copyTC(ThreadContext *context);
 136
 137     void copyState(ThreadContext *oldContext);
 138
 139     void serialize(std::ostream &os);
 140     void unserialize(Checkpoint *cp, const std::string &section);
 141
 142     /***************************************************************
 143      *  SimpleThread functions to provide CPU with access to various
 144      *  state, and to provide address translation methods.
 145      **************************************************************/
 146
 147     /** Returns the pointer to this SimpleThread's ThreadContext. Used
 148      *  when a ThreadContext must be passed to objects outside of the
 149      *  CPU.
 150      */
 151     ThreadContext *getTC() { return tc; }
 152
 153 #if FULL_SYSTEM
 154     int getInstAsid() { return regs.instAsid(); }
 155     int getDataAsid() { return regs.dataAsid(); }
 156
 157     Fault translateInstReq(RequestPtr &req)
 158     {
 159         return itb->translate(req, tc);
 160     }
 161
 162     Fault translateDataReadReq(RequestPtr &req)
 163     {
 164         return dtb->translate(req, tc, false);
 165     }
 166
 167     Fault translateDataWriteReq(RequestPtr &req)
 168     {
 169         return dtb->translate(req, tc, true);
 170     }
 171
 172     void dumpFuncProfile();
 173
 174     Fault hwrei();
 175
 176     bool simPalCheck(int palFunc);
 177 #else
 178
 179     Fault translateInstReq(RequestPtr &req)
 180     {
 181         return process->pTable->translate(req);
 182     }
 183
 184     Fault translateDataReadReq(RequestPtr &req)
 185     {
 186         return process->pTable->translate(req);
 187     }
 188
 189     Fault translateDataWriteReq(RequestPtr &req)
 190     {
 191         return process->pTable->translate(req);
 192     }
 193 #endif
 194
 195     /*******************************************
 196      * ThreadContext interface functions.
 197      ******************************************/
 198
 199     BaseCPU *getCpuPtr() { return cpu; }
 200
 201     int getThreadNum() { return tid; }
 202
 203 #if FULL_SYSTEM
 204     System *getSystemPtr() { return system; }
 205
 206     TheISA::ITB *getITBPtr() { return itb; }
 207
 208     TheISA::DTB *getDTBPtr() { return dtb; }
 209
 210     FunctionalPort *getPhysPort() { return physPort; }
 211
 212     /** Return a virtual port. If no thread context is specified then a static
 213      * port is returned. Otherwise a port is created and returned. It must be
 214      * deleted by deleteVirtPort(). */
 215     VirtualPort *getVirtPort(ThreadContext *tc);
 216
 217     void delVirtPort(VirtualPort *vp);
 218 #endif
 219
 220     Status status() const { return _status; }
 221
 222     void setStatus(Status newStatus) { _status = newStatus; }
 223
 224     /// Set the status to Active.  Optional delay indicates number of
 225     /// cycles to wait before beginning execution.
 226     void activate(int delay = 1);
 227
 228     /// Set the status to Suspended.
 229     void suspend();
 230
 231     /// Set the status to Unallocated.
 232     void deallocate();
 233
 234     /// Set the status to Halted.
 235     void halt();
 236
 237     virtual bool misspeculating();
 238
 239     Fault instRead(RequestPtr &req)
 240     {
 241         panic("instRead not implemented");
 242         // return funcPhysMem->read(req, inst);
 243         return NoFault;
 244     }
 245
 246     void copyArchRegs(ThreadContext *tc);
 247
 248     void clearArchRegs() { regs.clear(); }
 249
 250     //
 251     // New accessors for new decoder.
 252     //
 253     uint64_t readIntReg(int reg_idx)
 254     {
 255         return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx));
 256     }
 257
 258     FloatReg readFloatReg(int reg_idx, int width)
 259     {
 260         return regs.readFloatReg(reg_idx, width);
 261     }
 262
 263     FloatReg readFloatReg(int reg_idx)
 264     {
 265         return regs.readFloatReg(reg_idx);
 266     }
 267
 268     FloatRegBits readFloatRegBits(int reg_idx, int width)
 269     {
 270         return regs.readFloatRegBits(reg_idx, width);
 271     }
 272
 273     FloatRegBits readFloatRegBits(int reg_idx)
 274     {
 275         return regs.readFloatRegBits(reg_idx);
 276     }
 277
 278     void setIntReg(int reg_idx, uint64_t val)
 279     {
 280         regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val);
 281     }
 282
 283     void setFloatReg(int reg_idx, FloatReg val, int width)
 284     {
 285         regs.setFloatReg(reg_idx, val, width);
 286     }
 287
 288     void setFloatReg(int reg_idx, FloatReg val)
 289     {
 290         regs.setFloatReg(reg_idx, val);
 291     }
 292
 293     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
 294     {
 295         regs.setFloatRegBits(reg_idx, val, width);
 296     }
 297
 298     void setFloatRegBits(int reg_idx, FloatRegBits val)
 299     {
 300         regs.setFloatRegBits(reg_idx, val);
 301     }
 302
 303     uint64_t readPC()
 304     {
 305         return regs.readPC();
 306     }
 307
 308     void setPC(uint64_t val)
 309     {
 310         regs.setPC(val);
 311     }
 312
 313     uint64_t readMicroPC()
 314     {
 315         return microPC;
 316     }
 317
 318     void setMicroPC(uint64_t val)
 319     {
 320         microPC = val;
 321     }
 322
 323     uint64_t readNextPC()
 324     {
 325         return regs.readNextPC();
 326     }
 327
 328     void setNextPC(uint64_t val)
 329     {
 330         regs.setNextPC(val);
 331     }
 332
 333     uint64_t readNextMicroPC()
 334     {
 335         return nextMicroPC;
 336     }
 337
 338     void setNextMicroPC(uint64_t val)
 339     {
 340         nextMicroPC = val;
 341     }
 342
 343     uint64_t readNextNPC()
 344     {
 345         return regs.readNextNPC();
 346     }
 347
 348     void setNextNPC(uint64_t val)
 349     {
 350         regs.setNextNPC(val);
 351     }
 352
 353     MiscReg readMiscReg(int misc_reg)
 354     {
 355         return regs.readMiscReg(misc_reg);
 356     }
 357
 358     MiscReg readMiscRegWithEffect(int misc_reg)
 359     {
 360         return regs.readMiscRegWithEffect(misc_reg, tc);
 361     }
 362
 363     void setMiscReg(int misc_reg, const MiscReg &val)
 364     {
 365         return regs.setMiscReg(misc_reg, val);
 366     }
 367
 368     void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 369     {
 370         return regs.setMiscRegWithEffect(misc_reg, val, tc);
 371     }
 372
 373     unsigned readStCondFailures() { return storeCondFailures; }
 374
 375     void setStCondFailures(unsigned sc_failures)
 376     { storeCondFailures = sc_failures; }
 377
 378 #if !FULL_SYSTEM
 379     TheISA::IntReg getSyscallArg(int i)
 380     {
 381         return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
 382                     TheISA::ArgumentReg0 + i));
 383     }
 384
 385     // used to shift args for indirect syscall
 386     void setSyscallArg(int i, TheISA::IntReg val)
 387     {
 388         regs.setIntReg(TheISA::flattenIntIndex(getTC(),
 389                     TheISA::ArgumentReg0 + i), val);
 390     }
 391
 392     void setSyscallReturn(SyscallReturn return_value)
 393     {
 394         TheISA::setSyscallReturn(return_value, getTC());
 395     }
 396
 397     void syscall(int64_t callnum)
 398     {
 399         process->syscall(callnum, tc);
 400     }
 401 #endif
 402
 403     void changeRegFileContext(TheISA::RegContextParam param,
 404             TheISA::RegContextVal val)
 405     {
 406         regs.changeContext(param, val);
 407     }
 408 };
 409
 410
 411 // for non-speculative execution context, spec_mode is always false
 412 inline bool
 413 SimpleThread::misspeculating()
 414 {
 415     return false;
 416 }
 417
 418 #endif // __CPU_CPU_EXEC_CONTEXT_HH__