src/cpu/simple_thread.hh

   1 /*
   2  * Copyright (c) 2001-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #ifndef __CPU_SIMPLE_THREAD_HH__
  33 #define __CPU_SIMPLE_THREAD_HH__
  34
  35 #include "arch/isa_traits.hh"
  36 #include "arch/regfile.hh"
  37 #include "arch/syscallreturn.hh"
  38 #include "arch/tlb.hh"
  39 #include "config/full_system.hh"
  40 #include "cpu/thread_context.hh"
  41 #include "cpu/thread_state.hh"
  42 #include "mem/request.hh"
  43 #include "sim/byteswap.hh"
  44 #include "sim/eventq.hh"
  45 #include "sim/host.hh"
  46 #include "sim/serialize.hh"
  47
  48 class BaseCPU;
  49
  50 #if FULL_SYSTEM
  51
  52 #include "sim/system.hh"
  53
  54 class FunctionProfile;
  55 class ProfileNode;
  56 class FunctionalPort;
  57 class PhysicalPort;
  58
  59 namespace TheISA {
  60     namespace Kernel {
  61         class Statistics;
  62     };
  63 };
  64
  65 #else // !FULL_SYSTEM
  66
  67 #include "sim/process.hh"
  68 #include "mem/page_table.hh"
  69 class TranslatingPort;
  70
  71 #endif // FULL_SYSTEM
  72
  73 /**
  74  * The SimpleThread object provides a combination of the ThreadState
  75  * object and the ThreadContext interface. It implements the
  76  * ThreadContext interface so that a ProxyThreadContext class can be
  77  * made using SimpleThread as the template parameter (see
  78  * thread_context.hh). It adds to the ThreadState object by adding all
  79  * the objects needed for simple functional execution, including a
  80  * simple architectural register file, and pointers to the ITB and DTB
  81  * in full system mode. For CPU models that do not need more advanced
  82  * ways to hold state (i.e. a separate physical register file, or
  83  * separate fetch and commit PC's), this SimpleThread class provides
  84  * all the necessary state for full architecture-level functional
  85  * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
  86  * examples.
  87  */
  88
  89 class SimpleThread : public ThreadState
  90 {
  91   protected:
  92     typedef TheISA::RegFile RegFile;
  93     typedef TheISA::MachInst MachInst;
  94     typedef TheISA::MiscRegFile MiscRegFile;
  95     typedef TheISA::MiscReg MiscReg;
  96     typedef TheISA::FloatReg FloatReg;
  97     typedef TheISA::FloatRegBits FloatRegBits;
  98   public:
  99     typedef ThreadContext::Status Status;
 100
 101   protected:
 102     RegFile regs;       // correct-path register context
 103
 104   public:
 105     // pointer to CPU associated with this SimpleThread
 106     BaseCPU *cpu;
 107
 108     ProxyThreadContext<SimpleThread> *tc;
 109
 110     System *system;
 111
 112     TheISA::ITB *itb;
 113     TheISA::DTB *dtb;
 114
 115     // constructor: initialize SimpleThread from given process structure
 116 #if FULL_SYSTEM
 117     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
 118                  TheISA::ITB *_itb, TheISA::DTB *_dtb,
 119                  bool use_kernel_stats = true);
 120 #else
 121     SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
 122                  TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid);
 123 #endif
 124
 125     SimpleThread();
 126
 127     virtual ~SimpleThread();
 128
 129     virtual void takeOverFrom(ThreadContext *oldContext);
 130
 131     void regStats(const std::string &name);
 132
 133     void copyTC(ThreadContext *context);
 134
 135     void copyState(ThreadContext *oldContext);
 136
 137     void serialize(std::ostream &os);
 138     void unserialize(Checkpoint *cp, const std::string &section);
 139
 140     /***************************************************************
 141      *  SimpleThread functions to provide CPU with access to various
 142      *  state, and to provide address translation methods.
 143      **************************************************************/
 144
 145     /** Returns the pointer to this SimpleThread's ThreadContext. Used
 146      *  when a ThreadContext must be passed to objects outside of the
 147      *  CPU.
 148      */
 149     ThreadContext *getTC() { return tc; }
 150
 151     Fault translateInstReq(RequestPtr &req)
 152     {
 153         return itb->translate(req, tc);
 154     }
 155
 156     Fault translateDataReadReq(RequestPtr &req)
 157     {
 158         return dtb->translate(req, tc, false);
 159     }
 160
 161     Fault translateDataWriteReq(RequestPtr &req)
 162     {
 163         return dtb->translate(req, tc, true);
 164     }
 165
 166     void demapPage(Addr vaddr, uint64_t asn)
 167     {
 168         itb->demapPage(vaddr, asn);
 169         dtb->demapPage(vaddr, asn);
 170     }
 171
 172     void demapInstPage(Addr vaddr, uint64_t asn)
 173     {
 174         itb->demapPage(vaddr, asn);
 175     }
 176
 177     void demapDataPage(Addr vaddr, uint64_t asn)
 178     {
 179         dtb->demapPage(vaddr, asn);
 180     }
 181
 182 #if FULL_SYSTEM
 183     int getInstAsid() { return regs.instAsid(); }
 184     int getDataAsid() { return regs.dataAsid(); }
 185
 186     void dumpFuncProfile();
 187
 188     Fault hwrei();
 189
 190     bool simPalCheck(int palFunc);
 191
 192 #endif
 193
 194     /*******************************************
 195      * ThreadContext interface functions.
 196      ******************************************/
 197
 198     BaseCPU *getCpuPtr() { return cpu; }
 199
 200     int getThreadNum() { return tid; }
 201
 202     TheISA::ITB *getITBPtr() { return itb; }
 203
 204     TheISA::DTB *getDTBPtr() { return dtb; }
 205
 206 #if FULL_SYSTEM
 207     System *getSystemPtr() { return system; }
 208
 209     FunctionalPort *getPhysPort() { return physPort; }
 210
 211     /** Return a virtual port. If no thread context is specified then a static
 212      * port is returned. Otherwise a port is created and returned. It must be
 213      * deleted by deleteVirtPort(). */
 214     VirtualPort *getVirtPort(ThreadContext *tc);
 215
 216     void delVirtPort(VirtualPort *vp);
 217 #endif
 218
 219     Status status() const { return _status; }
 220
 221     void setStatus(Status newStatus) { _status = newStatus; }
 222
 223     /// Set the status to Active.  Optional delay indicates number of
 224     /// cycles to wait before beginning execution.
 225     void activate(int delay = 1);
 226
 227     /// Set the status to Suspended.
 228     void suspend();
 229
 230     /// Set the status to Unallocated.
 231     void deallocate();
 232
 233     /// Set the status to Halted.
 234     void halt();
 235
 236     virtual bool misspeculating();
 237
 238     Fault instRead(RequestPtr &req)
 239     {
 240         panic("instRead not implemented");
 241         // return funcPhysMem->read(req, inst);
 242         return NoFault;
 243     }
 244
 245     void copyArchRegs(ThreadContext *tc);
 246
 247     void clearArchRegs() { regs.clear(); }
 248
 249     //
 250     // New accessors for new decoder.
 251     //
 252     uint64_t readIntReg(int reg_idx)
 253     {
 254         int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
 255         return regs.readIntReg(flatIndex);
 256     }
 257
 258     FloatReg readFloatReg(int reg_idx, int width)
 259     {
 260         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 261         return regs.readFloatReg(flatIndex, width);
 262     }
 263
 264     FloatReg readFloatReg(int reg_idx)
 265     {
 266         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 267         return regs.readFloatReg(flatIndex);
 268     }
 269
 270     FloatRegBits readFloatRegBits(int reg_idx, int width)
 271     {
 272         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 273         return regs.readFloatRegBits(flatIndex, width);
 274     }
 275
 276     FloatRegBits readFloatRegBits(int reg_idx)
 277     {
 278         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 279         return regs.readFloatRegBits(flatIndex);
 280     }
 281
 282     void setIntReg(int reg_idx, uint64_t val)
 283     {
 284         int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
 285         regs.setIntReg(flatIndex, val);
 286     }
 287
 288     void setFloatReg(int reg_idx, FloatReg val, int width)
 289     {
 290         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 291         regs.setFloatReg(flatIndex, val, width);
 292     }
 293
 294     void setFloatReg(int reg_idx, FloatReg val)
 295     {
 296         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 297         regs.setFloatReg(flatIndex, val);
 298     }
 299
 300     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
 301     {
 302         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 303         regs.setFloatRegBits(flatIndex, val, width);
 304     }
 305
 306     void setFloatRegBits(int reg_idx, FloatRegBits val)
 307     {
 308         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 309         regs.setFloatRegBits(flatIndex, val);
 310     }
 311
 312     uint64_t readPC()
 313     {
 314         return regs.readPC();
 315     }
 316
 317     void setPC(uint64_t val)
 318     {
 319         regs.setPC(val);
 320     }
 321
 322     uint64_t readMicroPC()
 323     {
 324         return microPC;
 325     }
 326
 327     void setMicroPC(uint64_t val)
 328     {
 329         microPC = val;
 330     }
 331
 332     uint64_t readNextPC()
 333     {
 334         return regs.readNextPC();
 335     }
 336
 337     void setNextPC(uint64_t val)
 338     {
 339         regs.setNextPC(val);
 340     }
 341
 342     uint64_t readNextMicroPC()
 343     {
 344         return nextMicroPC;
 345     }
 346
 347     void setNextMicroPC(uint64_t val)
 348     {
 349         nextMicroPC = val;
 350     }
 351
 352     uint64_t readNextNPC()
 353     {
 354         return regs.readNextNPC();
 355     }
 356
 357     void setNextNPC(uint64_t val)
 358     {
 359         regs.setNextNPC(val);
 360     }
 361
 362     MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
 363     {
 364         return regs.readMiscRegNoEffect(misc_reg);
 365     }
 366
 367     MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
 368     {
 369         return regs.readMiscReg(misc_reg, tc);
 370     }
 371
 372     void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
 373     {
 374         return regs.setMiscRegNoEffect(misc_reg, val);
 375     }
 376
 377     void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
 378     {
 379         return regs.setMiscReg(misc_reg, val, tc);
 380     }
 381
 382     unsigned readStCondFailures() { return storeCondFailures; }
 383
 384     void setStCondFailures(unsigned sc_failures)
 385     { storeCondFailures = sc_failures; }
 386
 387 #if !FULL_SYSTEM
 388     TheISA::IntReg getSyscallArg(int i)
 389     {
 390         assert(i < TheISA::NumArgumentRegs);
 391         return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
 392                     TheISA::ArgumentReg[i]));
 393     }
 394
 395     // used to shift args for indirect syscall
 396     void setSyscallArg(int i, TheISA::IntReg val)
 397     {
 398         assert(i < TheISA::NumArgumentRegs);
 399         regs.setIntReg(TheISA::flattenIntIndex(getTC(),
 400                     TheISA::ArgumentReg[i]), val);
 401     }
 402
 403     void setSyscallReturn(SyscallReturn return_value)
 404     {
 405         TheISA::setSyscallReturn(return_value, getTC());
 406     }
 407
 408     void syscall(int64_t callnum)
 409     {
 410         process->syscall(callnum, tc);
 411     }
 412 #endif
 413
 414     void changeRegFileContext(TheISA::RegContextParam param,
 415             TheISA::RegContextVal val)
 416     {
 417         regs.changeContext(param, val);
 418     }
 419 };
 420
 421
 422 // for non-speculative execution context, spec_mode is always false
 423 inline bool
 424 SimpleThread::misspeculating()
 425 {
 426     return false;
 427 }
 428
 429 #endif // __CPU_CPU_EXEC_CONTEXT_HH__