2 * Copyright (c) 2011 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2001-2006 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Steve Reinhardt
44 #ifndef __CPU_SIMPLE_THREAD_HH__
45 #define __CPU_SIMPLE_THREAD_HH__
47 #include "arch/decoder.hh"
48 #include "arch/isa.hh"
49 #include "arch/isa_traits.hh"
50 #include "arch/registers.hh"
51 #include "arch/tlb.hh"
52 #include "arch/types.hh"
53 #include "base/types.hh"
54 #include "config/the_isa.hh"
55 #include "cpu/thread_context.hh"
56 #include "cpu/thread_state.hh"
57 #include "debug/FloatRegs.hh"
58 #include "debug/IntRegs.hh"
59 #include "mem/page_table.hh"
60 #include "mem/request.hh"
61 #include "sim/byteswap.hh"
62 #include "sim/eventq.hh"
63 #include "sim/process.hh"
64 #include "sim/serialize.hh"
65 #include "sim/system.hh"
70 class FunctionProfile;
80 * The SimpleThread object provides a combination of the ThreadState
81 * object and the ThreadContext interface. It implements the
82 * ThreadContext interface so that a ProxyThreadContext class can be
83 * made using SimpleThread as the template parameter (see
84 * thread_context.hh). It adds to the ThreadState object by adding all
85 * the objects needed for simple functional execution, including a
86 * simple architectural register file, and pointers to the ITB and DTB
87 * in full system mode. For CPU models that do not need more advanced
88 * ways to hold state (i.e. a separate physical register file, or
89 * separate fetch and commit PC's), this SimpleThread class provides
90 * all the necessary state for full architecture-level functional
91 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
95 class SimpleThread : public ThreadState
98 typedef TheISA::MachInst MachInst;
99 typedef TheISA::MiscReg MiscReg;
100 typedef TheISA::FloatReg FloatReg;
101 typedef TheISA::FloatRegBits FloatRegBits;
103 typedef ThreadContext::Status Status;
107 FloatReg f[TheISA::NumFloatRegs];
108 FloatRegBits i[TheISA::NumFloatRegs];
110 TheISA::IntReg intRegs[TheISA::NumIntRegs];
111 TheISA::ISA *const isa; // one "instance" of the current ISA.
113 TheISA::PCState _pcState;
115 /** Did this instruction execute or is it predicated false */
119 std::string name() const
121 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
124 ProxyThreadContext<SimpleThread> *tc;
131 TheISA::Decoder decoder;
133 // constructor: initialize SimpleThread from given process structure
135 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
136 TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa,
137 bool use_kernel_stats = true);
139 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
140 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb,
143 virtual ~SimpleThread();
145 virtual void takeOverFrom(ThreadContext *oldContext);
147 void regStats(const std::string &name);
149 void copyState(ThreadContext *oldContext);
151 void serialize(std::ostream &os);
152 void unserialize(Checkpoint *cp, const std::string §ion);
155 /***************************************************************
156 * SimpleThread functions to provide CPU with access to various
158 **************************************************************/
160 /** Returns the pointer to this SimpleThread's ThreadContext. Used
161 * when a ThreadContext must be passed to objects outside of the
164 ThreadContext *getTC() { return tc; }
166 void demapPage(Addr vaddr, uint64_t asn)
168 itb->demapPage(vaddr, asn);
169 dtb->demapPage(vaddr, asn);
172 void demapInstPage(Addr vaddr, uint64_t asn)
174 itb->demapPage(vaddr, asn);
177 void demapDataPage(Addr vaddr, uint64_t asn)
179 dtb->demapPage(vaddr, asn);
182 void dumpFuncProfile();
186 bool simPalCheck(int palFunc);
188 /*******************************************
189 * ThreadContext interface functions.
190 ******************************************/
192 BaseCPU *getCpuPtr() { return baseCpu; }
194 TheISA::TLB *getITBPtr() { return itb; }
196 TheISA::TLB *getDTBPtr() { return dtb; }
198 CheckerCPU *getCheckerCpuPtr() { return NULL; }
200 TheISA::Decoder *getDecoderPtr() { return &decoder; }
202 System *getSystemPtr() { return system; }
204 Status status() const { return _status; }
206 void setStatus(Status newStatus) { _status = newStatus; }
208 /// Set the status to Active. Optional delay indicates number of
209 /// cycles to wait before beginning execution.
210 void activate(Cycles delay = Cycles(1));
212 /// Set the status to Suspended.
215 /// Set the status to Halted.
218 virtual bool misspeculating();
220 void copyArchRegs(ThreadContext *tc);
225 memset(intRegs, 0, sizeof(intRegs));
226 memset(floatRegs.i, 0, sizeof(floatRegs.i));
231 // New accessors for new decoder.
233 uint64_t readIntReg(int reg_idx)
235 int flatIndex = isa->flattenIntIndex(reg_idx);
236 assert(flatIndex < TheISA::NumIntRegs);
237 uint64_t regVal(readIntRegFlat(flatIndex));
238 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
239 reg_idx, flatIndex, regVal);
243 FloatReg readFloatReg(int reg_idx)
245 int flatIndex = isa->flattenFloatIndex(reg_idx);
246 assert(flatIndex < TheISA::NumFloatRegs);
247 FloatReg regVal(readFloatRegFlat(flatIndex));
248 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
249 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
253 FloatRegBits readFloatRegBits(int reg_idx)
255 int flatIndex = isa->flattenFloatIndex(reg_idx);
256 assert(flatIndex < TheISA::NumFloatRegs);
257 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
258 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
259 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
263 void setIntReg(int reg_idx, uint64_t val)
265 int flatIndex = isa->flattenIntIndex(reg_idx);
266 assert(flatIndex < TheISA::NumIntRegs);
267 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
268 reg_idx, flatIndex, val);
269 setIntRegFlat(flatIndex, val);
272 void setFloatReg(int reg_idx, FloatReg val)
274 int flatIndex = isa->flattenFloatIndex(reg_idx);
275 assert(flatIndex < TheISA::NumFloatRegs);
276 setFloatRegFlat(flatIndex, val);
277 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
278 reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
281 void setFloatRegBits(int reg_idx, FloatRegBits val)
283 int flatIndex = isa->flattenFloatIndex(reg_idx);
284 assert(flatIndex < TheISA::NumFloatRegs);
285 // XXX: Fix array out of bounds compiler error for gem5.fast
286 // when checkercpu enabled
287 if (flatIndex < TheISA::NumFloatRegs)
288 setFloatRegBitsFlat(flatIndex, val);
289 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
290 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
300 pcState(const TheISA::PCState &val)
306 pcStateNoRecord(const TheISA::PCState &val)
314 return _pcState.instAddr();
320 return _pcState.nextInstAddr();
326 return _pcState.microPC();
334 void setPredicate(bool val)
340 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
342 return isa->readMiscRegNoEffect(misc_reg);
346 readMiscReg(int misc_reg, ThreadID tid = 0)
348 return isa->readMiscReg(misc_reg, tc);
352 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
354 return isa->setMiscRegNoEffect(misc_reg, val);
358 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
360 return isa->setMiscReg(misc_reg, val, tc);
364 flattenIntIndex(int reg)
366 return isa->flattenIntIndex(reg);
370 flattenFloatIndex(int reg)
372 return isa->flattenFloatIndex(reg);
375 unsigned readStCondFailures() { return storeCondFailures; }
377 void setStCondFailures(unsigned sc_failures)
378 { storeCondFailures = sc_failures; }
380 void syscall(int64_t callnum)
382 process->syscall(callnum, tc);
385 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
386 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
388 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; }
389 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; }
391 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
392 void setFloatRegBitsFlat(int idx, FloatRegBits val) {
393 floatRegs.i[idx] = val;
399 // for non-speculative execution context, spec_mode is always false
401 SimpleThread::misspeculating()
406 #endif // __CPU_CPU_EXEC_CONTEXT_HH__