src/cpu/simple_thread.hh

   1 /*
   2  * Copyright (c) 2001-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #ifndef __CPU_SIMPLE_THREAD_HH__
  33 #define __CPU_SIMPLE_THREAD_HH__
  34
  35 #include "arch/isa_traits.hh"
  36 #include "arch/regfile.hh"
  37 #include "arch/syscallreturn.hh"
  38 #include "arch/tlb.hh"
  39 #include "config/full_system.hh"
  40 #include "cpu/thread_context.hh"
  41 #include "cpu/thread_state.hh"
  42 #include "mem/request.hh"
  43 #include "sim/byteswap.hh"
  44 #include "sim/eventq.hh"
  45 #include "sim/host.hh"
  46 #include "sim/serialize.hh"
  47
  48 class BaseCPU;
  49
  50 #if FULL_SYSTEM
  51
  52 #include "sim/system.hh"
  53
  54 class FunctionProfile;
  55 class ProfileNode;
  56 class FunctionalPort;
  57 class PhysicalPort;
  58
  59 namespace TheISA {
  60     namespace Kernel {
  61         class Statistics;
  62     };
  63 };
  64
  65 #else // !FULL_SYSTEM
  66
  67 #include "sim/process.hh"
  68 #include "mem/page_table.hh"
  69 class TranslatingPort;
  70
  71 #endif // FULL_SYSTEM
  72
  73 /**
  74  * The SimpleThread object provides a combination of the ThreadState
  75  * object and the ThreadContext interface. It implements the
  76  * ThreadContext interface so that a ProxyThreadContext class can be
  77  * made using SimpleThread as the template parameter (see
  78  * thread_context.hh). It adds to the ThreadState object by adding all
  79  * the objects needed for simple functional execution, including a
  80  * simple architectural register file, and pointers to the ITB and DTB
  81  * in full system mode. For CPU models that do not need more advanced
  82  * ways to hold state (i.e. a separate physical register file, or
  83  * separate fetch and commit PC's), this SimpleThread class provides
  84  * all the necessary state for full architecture-level functional
  85  * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
  86  * examples.
  87  */
  88
  89 class SimpleThread : public ThreadState
  90 {
  91   protected:
  92     typedef TheISA::RegFile RegFile;
  93     typedef TheISA::MachInst MachInst;
  94     typedef TheISA::MiscRegFile MiscRegFile;
  95     typedef TheISA::MiscReg MiscReg;
  96     typedef TheISA::FloatReg FloatReg;
  97     typedef TheISA::FloatRegBits FloatRegBits;
  98   public:
  99     typedef ThreadContext::Status Status;
 100
 101   protected:
 102     RegFile regs;       // correct-path register context
 103
 104   public:
 105     // pointer to CPU associated with this SimpleThread
 106     BaseCPU *cpu;
 107
 108     ProxyThreadContext<SimpleThread> *tc;
 109
 110     System *system;
 111
 112     TheISA::ITB *itb;
 113     TheISA::DTB *dtb;
 114
 115     // constructor: initialize SimpleThread from given process structure
 116 #if FULL_SYSTEM
 117     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
 118                  TheISA::ITB *_itb, TheISA::DTB *_dtb,
 119                  bool use_kernel_stats = true);
 120 #else
 121     SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
 122                  TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid);
 123 #endif
 124
 125     SimpleThread();
 126
 127     virtual ~SimpleThread();
 128
 129     virtual void takeOverFrom(ThreadContext *oldContext);
 130
 131     void regStats(const std::string &name);
 132
 133     void copyTC(ThreadContext *context);
 134
 135     void copyState(ThreadContext *oldContext);
 136
 137     void serialize(std::ostream &os);
 138     void unserialize(Checkpoint *cp, const std::string &section);
 139
 140     /***************************************************************
 141      *  SimpleThread functions to provide CPU with access to various
 142      *  state.
 143      **************************************************************/
 144
 145     /** Returns the pointer to this SimpleThread's ThreadContext. Used
 146      *  when a ThreadContext must be passed to objects outside of the
 147      *  CPU.
 148      */
 149     ThreadContext *getTC() { return tc; }
 150
 151     void demapPage(Addr vaddr, uint64_t asn)
 152     {
 153         itb->demapPage(vaddr, asn);
 154         dtb->demapPage(vaddr, asn);
 155     }
 156
 157     void demapInstPage(Addr vaddr, uint64_t asn)
 158     {
 159         itb->demapPage(vaddr, asn);
 160     }
 161
 162     void demapDataPage(Addr vaddr, uint64_t asn)
 163     {
 164         dtb->demapPage(vaddr, asn);
 165     }
 166
 167 #if FULL_SYSTEM
 168     int getInstAsid() { return regs.instAsid(); }
 169     int getDataAsid() { return regs.dataAsid(); }
 170
 171     void dumpFuncProfile();
 172
 173     Fault hwrei();
 174
 175     bool simPalCheck(int palFunc);
 176
 177 #endif
 178
 179     /*******************************************
 180      * ThreadContext interface functions.
 181      ******************************************/
 182
 183     BaseCPU *getCpuPtr() { return cpu; }
 184
 185     TheISA::ITB *getITBPtr() { return itb; }
 186
 187     TheISA::DTB *getDTBPtr() { return dtb; }
 188
 189     System *getSystemPtr() { return system; }
 190
 191 #if FULL_SYSTEM
 192     FunctionalPort *getPhysPort() { return physPort; }
 193
 194     /** Return a virtual port. This port cannot be cached locally in an object.
 195      * After a CPU switch it may point to the wrong memory object which could
 196      * mean stale data.
 197      */
 198     VirtualPort *getVirtPort() { return virtPort; }
 199 #endif
 200
 201     Status status() const { return _status; }
 202
 203     void setStatus(Status newStatus) { _status = newStatus; }
 204
 205     /// Set the status to Active.  Optional delay indicates number of
 206     /// cycles to wait before beginning execution.
 207     void activate(int delay = 1);
 208
 209     /// Set the status to Suspended.
 210     void suspend();
 211
 212     /// Set the status to Unallocated.
 213     void deallocate();
 214
 215     /// Set the status to Halted.
 216     void halt();
 217
 218     virtual bool misspeculating();
 219
 220     Fault instRead(RequestPtr &req)
 221     {
 222         panic("instRead not implemented");
 223         // return funcPhysMem->read(req, inst);
 224         return NoFault;
 225     }
 226
 227     void copyArchRegs(ThreadContext *tc);
 228
 229     void clearArchRegs() { regs.clear(); }
 230
 231     //
 232     // New accessors for new decoder.
 233     //
 234     uint64_t readIntReg(int reg_idx)
 235     {
 236         int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
 237         return regs.readIntReg(flatIndex);
 238     }
 239
 240     FloatReg readFloatReg(int reg_idx, int width)
 241     {
 242         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 243         return regs.readFloatReg(flatIndex, width);
 244     }
 245
 246     FloatReg readFloatReg(int reg_idx)
 247     {
 248         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 249         return regs.readFloatReg(flatIndex);
 250     }
 251
 252     FloatRegBits readFloatRegBits(int reg_idx, int width)
 253     {
 254         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 255         return regs.readFloatRegBits(flatIndex, width);
 256     }
 257
 258     FloatRegBits readFloatRegBits(int reg_idx)
 259     {
 260         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 261         return regs.readFloatRegBits(flatIndex);
 262     }
 263
 264     void setIntReg(int reg_idx, uint64_t val)
 265     {
 266         int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
 267         regs.setIntReg(flatIndex, val);
 268     }
 269
 270     void setFloatReg(int reg_idx, FloatReg val, int width)
 271     {
 272         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 273         regs.setFloatReg(flatIndex, val, width);
 274     }
 275
 276     void setFloatReg(int reg_idx, FloatReg val)
 277     {
 278         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 279         regs.setFloatReg(flatIndex, val);
 280     }
 281
 282     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
 283     {
 284         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 285         regs.setFloatRegBits(flatIndex, val, width);
 286     }
 287
 288     void setFloatRegBits(int reg_idx, FloatRegBits val)
 289     {
 290         int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
 291         regs.setFloatRegBits(flatIndex, val);
 292     }
 293
 294     uint64_t readPC()
 295     {
 296         return regs.readPC();
 297     }
 298
 299     void setPC(uint64_t val)
 300     {
 301         regs.setPC(val);
 302     }
 303
 304     uint64_t readMicroPC()
 305     {
 306         return microPC;
 307     }
 308
 309     void setMicroPC(uint64_t val)
 310     {
 311         microPC = val;
 312     }
 313
 314     uint64_t readNextPC()
 315     {
 316         return regs.readNextPC();
 317     }
 318
 319     void setNextPC(uint64_t val)
 320     {
 321         regs.setNextPC(val);
 322     }
 323
 324     uint64_t readNextMicroPC()
 325     {
 326         return nextMicroPC;
 327     }
 328
 329     void setNextMicroPC(uint64_t val)
 330     {
 331         nextMicroPC = val;
 332     }
 333
 334     uint64_t readNextNPC()
 335     {
 336         return regs.readNextNPC();
 337     }
 338
 339     void setNextNPC(uint64_t val)
 340     {
 341         regs.setNextNPC(val);
 342     }
 343
 344     MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
 345     {
 346         return regs.readMiscRegNoEffect(misc_reg);
 347     }
 348
 349     MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
 350     {
 351         return regs.readMiscReg(misc_reg, tc);
 352     }
 353
 354     void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
 355     {
 356         return regs.setMiscRegNoEffect(misc_reg, val);
 357     }
 358
 359     void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
 360     {
 361         return regs.setMiscReg(misc_reg, val, tc);
 362     }
 363
 364     unsigned readStCondFailures() { return storeCondFailures; }
 365
 366     void setStCondFailures(unsigned sc_failures)
 367     { storeCondFailures = sc_failures; }
 368
 369 #if !FULL_SYSTEM
 370     TheISA::IntReg getSyscallArg(int i)
 371     {
 372         assert(i < TheISA::NumArgumentRegs);
 373         TheISA::IntReg val = regs.readIntReg(
 374                 TheISA::flattenIntIndex(getTC(), TheISA::ArgumentReg[i]));
 375 #if THE_ISA == SPARC_ISA
 376         if (bits(this->readMiscRegNoEffect(
 377                         SparcISA::MISCREG_PSTATE), 3, 3)) {
 378             val = bits(val, 31, 0);
 379         }
 380 #endif
 381         return val;
 382     }
 383
 384     // used to shift args for indirect syscall
 385     void setSyscallArg(int i, TheISA::IntReg val)
 386     {
 387         assert(i < TheISA::NumArgumentRegs);
 388         regs.setIntReg(TheISA::flattenIntIndex(getTC(),
 389                     TheISA::ArgumentReg[i]), val);
 390     }
 391
 392     void setSyscallReturn(SyscallReturn return_value)
 393     {
 394         TheISA::setSyscallReturn(return_value, getTC());
 395     }
 396
 397     void syscall(int64_t callnum)
 398     {
 399         process->syscall(callnum, tc);
 400     }
 401 #endif
 402 };
 403
 404
 405 // for non-speculative execution context, spec_mode is always false
 406 inline bool
 407 SimpleThread::misspeculating()
 408 {
 409     return false;
 410 }
 411
 412 #endif // __CPU_CPU_EXEC_CONTEXT_HH__