2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #ifndef __CPU_SIMPLE_THREAD_HH__
33 #define __CPU_SIMPLE_THREAD_HH__
35 #include "arch/isa_traits.hh"
36 #include "arch/regfile.hh"
37 #include "arch/syscallreturn.hh"
38 #include "config/full_system.hh"
39 #include "cpu/thread_context.hh"
40 #include "cpu/thread_state.hh"
41 #include "mem/request.hh"
42 #include "sim/byteswap.hh"
43 #include "sim/eventq.hh"
44 #include "sim/host.hh"
45 #include "sim/serialize.hh"
51 #include "sim/system.hh"
52 #include "arch/tlb.hh"
54 class FunctionProfile;
67 #include "sim/process.hh"
68 #include "mem/page_table.hh"
69 class TranslatingPort;
74 * The SimpleThread object provides a combination of the ThreadState
75 * object and the ThreadContext interface. It implements the
76 * ThreadContext interface so that a ProxyThreadContext class can be
77 * made using SimpleThread as the template parameter (see
78 * thread_context.hh). It adds to the ThreadState object by adding all
79 * the objects needed for simple functional execution, including a
80 * simple architectural register file, and pointers to the ITB and DTB
81 * in full system mode. For CPU models that do not need more advanced
82 * ways to hold state (i.e. a separate physical register file, or
83 * separate fetch and commit PC's), this SimpleThread class provides
84 * all the necessary state for full architecture-level functional
85 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
89 class SimpleThread : public ThreadState
92 typedef TheISA::RegFile RegFile;
93 typedef TheISA::MachInst MachInst;
94 typedef TheISA::MiscRegFile MiscRegFile;
95 typedef TheISA::MiscReg MiscReg;
96 typedef TheISA::FloatReg FloatReg;
97 typedef TheISA::FloatRegBits FloatRegBits;
99 typedef ThreadContext::Status Status;
102 RegFile regs; // correct-path register context
105 // pointer to CPU associated with this SimpleThread
108 ProxyThreadContext<SimpleThread> *tc;
117 // constructor: initialize SimpleThread from given process structure
119 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
120 TheISA::ITB *_itb, TheISA::DTB *_dtb,
121 bool use_kernel_stats = true);
123 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
128 virtual ~SimpleThread();
130 virtual void takeOverFrom(ThreadContext *oldContext);
132 void regStats(const std::string &name);
134 void copyTC(ThreadContext *context);
136 void copyState(ThreadContext *oldContext);
138 void serialize(std::ostream &os);
139 void unserialize(Checkpoint *cp, const std::string §ion);
141 /***************************************************************
142 * SimpleThread functions to provide CPU with access to various
143 * state, and to provide address translation methods.
144 **************************************************************/
146 /** Returns the pointer to this SimpleThread's ThreadContext. Used
147 * when a ThreadContext must be passed to objects outside of the
150 ThreadContext *getTC() { return tc; }
153 int getInstAsid() { return regs.instAsid(); }
154 int getDataAsid() { return regs.dataAsid(); }
156 Fault translateInstReq(RequestPtr &req)
158 return itb->translate(req, tc);
161 Fault translateDataReadReq(RequestPtr &req)
163 return dtb->translate(req, tc, false);
166 Fault translateDataWriteReq(RequestPtr &req)
168 return dtb->translate(req, tc, true);
171 void dumpFuncProfile();
175 bool simPalCheck(int palFunc);
178 Fault translateInstReq(RequestPtr &req)
180 return process->pTable->translate(req);
183 Fault translateDataReadReq(RequestPtr &req)
185 return process->pTable->translate(req);
188 Fault translateDataWriteReq(RequestPtr &req)
190 return process->pTable->translate(req);
194 /*******************************************
195 * ThreadContext interface functions.
196 ******************************************/
198 BaseCPU *getCpuPtr() { return cpu; }
200 int getThreadNum() { return tid; }
203 System *getSystemPtr() { return system; }
205 TheISA::ITB *getITBPtr() { return itb; }
207 TheISA::DTB *getDTBPtr() { return dtb; }
209 FunctionalPort *getPhysPort() { return physPort; }
211 /** Return a virtual port. If no thread context is specified then a static
212 * port is returned. Otherwise a port is created and returned. It must be
213 * deleted by deleteVirtPort(). */
214 VirtualPort *getVirtPort(ThreadContext *tc);
216 void delVirtPort(VirtualPort *vp);
219 Status status() const { return _status; }
221 void setStatus(Status newStatus) { _status = newStatus; }
223 /// Set the status to Active. Optional delay indicates number of
224 /// cycles to wait before beginning execution.
225 void activate(int delay = 1);
227 /// Set the status to Suspended.
230 /// Set the status to Unallocated.
233 /// Set the status to Halted.
236 virtual bool misspeculating();
238 Fault instRead(RequestPtr &req)
240 panic("instRead not implemented");
241 // return funcPhysMem->read(req, inst);
245 void copyArchRegs(ThreadContext *tc);
247 void clearArchRegs() { regs.clear(); }
250 // New accessors for new decoder.
252 uint64_t readIntReg(int reg_idx)
254 return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx));
257 FloatReg readFloatReg(int reg_idx, int width)
259 return regs.readFloatReg(reg_idx, width);
262 FloatReg readFloatReg(int reg_idx)
264 return regs.readFloatReg(reg_idx);
267 FloatRegBits readFloatRegBits(int reg_idx, int width)
269 return regs.readFloatRegBits(reg_idx, width);
272 FloatRegBits readFloatRegBits(int reg_idx)
274 return regs.readFloatRegBits(reg_idx);
277 void setIntReg(int reg_idx, uint64_t val)
279 regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val);
282 void setFloatReg(int reg_idx, FloatReg val, int width)
284 regs.setFloatReg(reg_idx, val, width);
287 void setFloatReg(int reg_idx, FloatReg val)
289 regs.setFloatReg(reg_idx, val);
292 void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
294 regs.setFloatRegBits(reg_idx, val, width);
297 void setFloatRegBits(int reg_idx, FloatRegBits val)
299 regs.setFloatRegBits(reg_idx, val);
304 return regs.readPC();
307 void setPC(uint64_t val)
312 uint64_t readMicroPC()
317 void setMicroPC(uint64_t val)
322 uint64_t readNextPC()
324 return regs.readNextPC();
327 void setNextPC(uint64_t val)
332 uint64_t readNextMicroPC()
337 void setNextMicroPC(uint64_t val)
342 uint64_t readNextNPC()
344 return regs.readNextNPC();
347 void setNextNPC(uint64_t val)
349 regs.setNextNPC(val);
352 MiscReg readMiscRegNoEffect(int misc_reg)
354 return regs.readMiscRegNoEffect(misc_reg);
357 MiscReg readMiscReg(int misc_reg)
359 return regs.readMiscReg(misc_reg, tc);
362 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
364 return regs.setMiscRegNoEffect(misc_reg, val);
367 void setMiscReg(int misc_reg, const MiscReg &val)
369 return regs.setMiscReg(misc_reg, val, tc);
372 unsigned readStCondFailures() { return storeCondFailures; }
374 void setStCondFailures(unsigned sc_failures)
375 { storeCondFailures = sc_failures; }
378 TheISA::IntReg getSyscallArg(int i)
380 return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
381 TheISA::ArgumentReg0 + i));
384 // used to shift args for indirect syscall
385 void setSyscallArg(int i, TheISA::IntReg val)
387 regs.setIntReg(TheISA::flattenIntIndex(getTC(),
388 TheISA::ArgumentReg0 + i), val);
391 void setSyscallReturn(SyscallReturn return_value)
393 TheISA::setSyscallReturn(return_value, getTC());
396 void syscall(int64_t callnum)
398 process->syscall(callnum, tc);
402 void changeRegFileContext(TheISA::RegContextParam param,
403 TheISA::RegContextVal val)
405 regs.changeContext(param, val);
410 // for non-speculative execution context, spec_mode is always false
412 SimpleThread::misspeculating()
417 #endif // __CPU_CPU_EXEC_CONTEXT_HH__