2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
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13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2001-2006 The Regents of The University of Michigan
16 * All rights reserved.
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19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
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27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
45 #ifndef __CPU_SIMPLE_THREAD_HH__
46 #define __CPU_SIMPLE_THREAD_HH__
48 #include "arch/decoder.hh"
49 #include "arch/isa.hh"
50 #include "arch/isa_traits.hh"
51 #include "arch/registers.hh"
52 #include "arch/tlb.hh"
53 #include "arch/types.hh"
54 #include "base/types.hh"
55 #include "config/the_isa.hh"
56 #include "cpu/thread_context.hh"
57 #include "cpu/thread_state.hh"
58 #include "debug/CCRegs.hh"
59 #include "debug/FloatRegs.hh"
60 #include "debug/IntRegs.hh"
61 #include "mem/page_table.hh"
62 #include "mem/request.hh"
63 #include "sim/byteswap.hh"
64 #include "sim/eventq.hh"
65 #include "sim/process.hh"
66 #include "sim/serialize.hh"
67 #include "sim/system.hh"
72 class FunctionProfile;
82 * The SimpleThread object provides a combination of the ThreadState
83 * object and the ThreadContext interface. It implements the
84 * ThreadContext interface so that a ProxyThreadContext class can be
85 * made using SimpleThread as the template parameter (see
86 * thread_context.hh). It adds to the ThreadState object by adding all
87 * the objects needed for simple functional execution, including a
88 * simple architectural register file, and pointers to the ITB and DTB
89 * in full system mode. For CPU models that do not need more advanced
90 * ways to hold state (i.e. a separate physical register file, or
91 * separate fetch and commit PC's), this SimpleThread class provides
92 * all the necessary state for full architecture-level functional
93 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
97 class SimpleThread : public ThreadState
100 typedef TheISA::MachInst MachInst;
101 typedef TheISA::MiscReg MiscReg;
102 typedef TheISA::FloatReg FloatReg;
103 typedef TheISA::FloatRegBits FloatRegBits;
104 typedef TheISA::CCReg CCReg;
106 typedef ThreadContext::Status Status;
110 FloatReg f[TheISA::NumFloatRegs];
111 FloatRegBits i[TheISA::NumFloatRegs];
113 TheISA::IntReg intRegs[TheISA::NumIntRegs];
114 #ifdef ISA_HAS_CC_REGS
115 TheISA::CCReg ccRegs[TheISA::NumCCRegs];
117 TheISA::ISA *const isa; // one "instance" of the current ISA.
119 TheISA::PCState _pcState;
121 /** Did this instruction execute or is it predicated false */
125 std::string name() const
127 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
130 ProxyThreadContext<SimpleThread> *tc;
137 TheISA::Decoder decoder;
139 // constructor: initialize SimpleThread from given process structure
141 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
142 TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa,
143 bool use_kernel_stats = true);
145 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
146 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb,
149 virtual ~SimpleThread();
151 virtual void takeOverFrom(ThreadContext *oldContext);
153 void regStats(const std::string &name);
155 void copyState(ThreadContext *oldContext);
157 void serialize(CheckpointOut &cp) const override;
158 void unserialize(CheckpointIn &cp) override;
161 /***************************************************************
162 * SimpleThread functions to provide CPU with access to various
164 **************************************************************/
166 /** Returns the pointer to this SimpleThread's ThreadContext. Used
167 * when a ThreadContext must be passed to objects outside of the
170 ThreadContext *getTC() { return tc; }
172 void demapPage(Addr vaddr, uint64_t asn)
174 itb->demapPage(vaddr, asn);
175 dtb->demapPage(vaddr, asn);
178 void demapInstPage(Addr vaddr, uint64_t asn)
180 itb->demapPage(vaddr, asn);
183 void demapDataPage(Addr vaddr, uint64_t asn)
185 dtb->demapPage(vaddr, asn);
188 void dumpFuncProfile();
192 bool simPalCheck(int palFunc);
194 /*******************************************
195 * ThreadContext interface functions.
196 ******************************************/
198 BaseCPU *getCpuPtr() { return baseCpu; }
200 TheISA::TLB *getITBPtr() { return itb; }
202 TheISA::TLB *getDTBPtr() { return dtb; }
204 CheckerCPU *getCheckerCpuPtr() { return NULL; }
206 TheISA::Decoder *getDecoderPtr() { return &decoder; }
208 System *getSystemPtr() { return system; }
210 Status status() const { return _status; }
212 void setStatus(Status newStatus) { _status = newStatus; }
214 /// Set the status to Active.
217 /// Set the status to Suspended.
220 /// Set the status to Halted.
223 void copyArchRegs(ThreadContext *tc);
228 memset(intRegs, 0, sizeof(intRegs));
229 memset(floatRegs.i, 0, sizeof(floatRegs.i));
230 #ifdef ISA_HAS_CC_REGS
231 memset(ccRegs, 0, sizeof(ccRegs));
237 // New accessors for new decoder.
239 uint64_t readIntReg(int reg_idx)
241 int flatIndex = isa->flattenIntIndex(reg_idx);
242 assert(flatIndex < TheISA::NumIntRegs);
243 uint64_t regVal(readIntRegFlat(flatIndex));
244 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
245 reg_idx, flatIndex, regVal);
249 FloatReg readFloatReg(int reg_idx)
251 int flatIndex = isa->flattenFloatIndex(reg_idx);
252 assert(flatIndex < TheISA::NumFloatRegs);
253 FloatReg regVal(readFloatRegFlat(flatIndex));
254 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
255 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
259 FloatRegBits readFloatRegBits(int reg_idx)
261 int flatIndex = isa->flattenFloatIndex(reg_idx);
262 assert(flatIndex < TheISA::NumFloatRegs);
263 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
264 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
265 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
269 CCReg readCCReg(int reg_idx)
271 #ifdef ISA_HAS_CC_REGS
272 int flatIndex = isa->flattenCCIndex(reg_idx);
273 assert(0 <= flatIndex);
274 assert(flatIndex < TheISA::NumCCRegs);
275 uint64_t regVal(readCCRegFlat(flatIndex));
276 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
277 reg_idx, flatIndex, regVal);
280 panic("Tried to read a CC register.");
285 void setIntReg(int reg_idx, uint64_t val)
287 int flatIndex = isa->flattenIntIndex(reg_idx);
288 assert(flatIndex < TheISA::NumIntRegs);
289 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
290 reg_idx, flatIndex, val);
291 setIntRegFlat(flatIndex, val);
294 void setFloatReg(int reg_idx, FloatReg val)
296 int flatIndex = isa->flattenFloatIndex(reg_idx);
297 assert(flatIndex < TheISA::NumFloatRegs);
298 setFloatRegFlat(flatIndex, val);
299 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
300 reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
303 void setFloatRegBits(int reg_idx, FloatRegBits val)
305 int flatIndex = isa->flattenFloatIndex(reg_idx);
306 assert(flatIndex < TheISA::NumFloatRegs);
307 // XXX: Fix array out of bounds compiler error for gem5.fast
308 // when checkercpu enabled
309 if (flatIndex < TheISA::NumFloatRegs)
310 setFloatRegBitsFlat(flatIndex, val);
311 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
312 reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
315 void setCCReg(int reg_idx, CCReg val)
317 #ifdef ISA_HAS_CC_REGS
318 int flatIndex = isa->flattenCCIndex(reg_idx);
319 assert(flatIndex < TheISA::NumCCRegs);
320 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
321 reg_idx, flatIndex, val);
322 setCCRegFlat(flatIndex, val);
324 panic("Tried to set a CC register.");
335 pcState(const TheISA::PCState &val)
341 pcStateNoRecord(const TheISA::PCState &val)
349 return _pcState.instAddr();
355 return _pcState.nextInstAddr();
361 return _pcState.microPC();
369 void setPredicate(bool val)
375 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
377 return isa->readMiscRegNoEffect(misc_reg);
381 readMiscReg(int misc_reg, ThreadID tid = 0)
383 return isa->readMiscReg(misc_reg, tc);
387 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
389 return isa->setMiscRegNoEffect(misc_reg, val);
393 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
395 return isa->setMiscReg(misc_reg, val, tc);
399 flattenIntIndex(int reg)
401 return isa->flattenIntIndex(reg);
405 flattenFloatIndex(int reg)
407 return isa->flattenFloatIndex(reg);
411 flattenCCIndex(int reg)
413 return isa->flattenCCIndex(reg);
417 flattenMiscIndex(int reg)
419 return isa->flattenMiscIndex(reg);
422 unsigned readStCondFailures() { return storeCondFailures; }
424 void setStCondFailures(unsigned sc_failures)
425 { storeCondFailures = sc_failures; }
427 void syscall(int64_t callnum, Fault *fault)
429 process->syscall(callnum, tc, fault);
432 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
433 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
435 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; }
436 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; }
438 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
439 void setFloatRegBitsFlat(int idx, FloatRegBits val) {
440 floatRegs.i[idx] = val;
443 #ifdef ISA_HAS_CC_REGS
444 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
445 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
447 CCReg readCCRegFlat(int idx)
448 { panic("readCCRegFlat w/no CC regs!\n"); }
450 void setCCRegFlat(int idx, CCReg val)
451 { panic("setCCRegFlat w/no CC regs!\n"); }
456 #endif // __CPU_CPU_EXEC_CONTEXT_HH__