src/cpu/static_inst.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #include <iostream>
  33
  34 #include "cpu/static_inst.hh"
  35 #include "sim/core.hh"
  36
  37 StaticInstPtr StaticInst::nullStaticInstPtr;
  38
  39 using namespace std;
  40
  41 StaticInst::~StaticInst()
  42 {
  43     if (cachedDisassembly)
  44         delete cachedDisassembly;
  45 }
  46
  47 bool
  48 StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
  49                             TheISA::PCState &tgt) const
  50 {
  51     if (isDirectCtrl()) {
  52         tgt = branchTarget(pc);
  53         return true;
  54     }
  55
  56     if (isIndirectCtrl()) {
  57         tgt = branchTarget(tc);
  58         return true;
  59     }
  60
  61     return false;
  62 }
  63
  64 StaticInstPtr
  65 StaticInst::fetchMicroop(MicroPC upc) const
  66 {
  67     panic("StaticInst::fetchMicroop() called on instruction "
  68           "that is not microcoded.");
  69 }
  70
  71 TheISA::PCState
  72 StaticInst::branchTarget(const TheISA::PCState &pc) const
  73 {
  74     panic("StaticInst::branchTarget() called on instruction "
  75           "that is not a PC-relative branch.");
  76     M5_DUMMY_RETURN;
  77 }
  78
  79 TheISA::PCState
  80 StaticInst::branchTarget(ThreadContext *tc) const
  81 {
  82     panic("StaticInst::branchTarget() called on instruction "
  83           "that is not an indirect branch.");
  84     M5_DUMMY_RETURN;
  85 }
  86
  87 const string &
  88 StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const
  89 {
  90     if (!cachedDisassembly)
  91         cachedDisassembly = new string(generateDisassembly(pc, symtab));
  92
  93     return *cachedDisassembly;
  94 }