src/cpu/static_inst.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #include <iostream>
  33 #include "cpu/static_inst.hh"
  34 #include "sim/core.hh"
  35
  36 StaticInstPtr StaticInst::nullStaticInstPtr;
  37
  38 // Define the decode cache hash map.
  39 StaticInst::DecodeCache StaticInst::decodeCache;
  40 StaticInst::AddrDecodeCache StaticInst::addrDecodeCache;
  41 StaticInst::cacheElement StaticInst::recentDecodes[2];
  42
  43 using namespace std;
  44
  45 StaticInst::~StaticInst()
  46 {
  47     if (cachedDisassembly)
  48         delete cachedDisassembly;
  49 }
  50
  51 void
  52 StaticInst::dumpDecodeCacheStats()
  53 {
  54     cerr << "Decode hash table stats @ " << curTick << ":" << endl;
  55     cerr << "\tnum entries = " << decodeCache.size() << endl;
  56     cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl;
  57     vector<int> hist(100, 0);
  58     int max_hist = 0;
  59     for (int i = 0; i < decodeCache.bucket_count(); ++i) {
  60         int count = decodeCache.elems_in_bucket(i);
  61         if (count > max_hist)
  62             max_hist = count;
  63         hist[count]++;
  64     }
  65     for (int i = 0; i <= max_hist; ++i) {
  66         cerr << "\tbuckets of size " << i << " = " << hist[i] << endl;
  67     }
  68 }
  69
  70 bool
  71 StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const
  72 {
  73     if (isDirectCtrl()) {
  74         tgt = branchTarget(pc);
  75         return true;
  76     }
  77
  78     if (isIndirectCtrl()) {
  79         tgt = branchTarget(tc);
  80         return true;
  81     }
  82
  83     return false;
  84 }
  85
  86 StaticInstPtr
  87 StaticInst::fetchMicroop(MicroPC micropc)
  88 {
  89     panic("StaticInst::fetchMicroop() called on instruction "
  90           "that is not microcoded.");
  91 }
  92
  93 Addr
  94 StaticInst::branchTarget(Addr branchPC) const
  95 {
  96     panic("StaticInst::branchTarget() called on instruction "
  97           "that is not a PC-relative branch.");
  98     M5_DUMMY_RETURN;
  99 }
 100
 101 Addr
 102 StaticInst::branchTarget(ThreadContext *tc) const
 103 {
 104     panic("StaticInst::branchTarget() called on instruction "
 105           "that is not an indirect branch.");
 106     M5_DUMMY_RETURN;
 107 }
 108
 109 const string &
 110 StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const
 111 {
 112     if (!cachedDisassembly)
 113         cachedDisassembly = new string(generateDisassembly(pc, symtab));
 114
 115     return *cachedDisassembly;
 116 }