2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
34 #include "cpu/static_inst.hh"
35 #include "sim/core.hh"
37 StaticInstPtr
StaticInst::nullStaticInstPtr
;
41 StaticInst::~StaticInst()
43 if (cachedDisassembly
)
44 delete cachedDisassembly
;
48 StaticInst::hasBranchTarget(const TheISA::PCState
&pc
, ThreadContext
*tc
,
49 TheISA::PCState
&tgt
) const
52 tgt
= branchTarget(pc
);
56 if (isIndirectCtrl()) {
57 tgt
= branchTarget(tc
);
65 StaticInst::fetchMicroop(MicroPC upc
) const
67 panic("StaticInst::fetchMicroop() called on instruction "
68 "that is not microcoded.");
72 StaticInst::branchTarget(const TheISA::PCState
&pc
) const
74 panic("StaticInst::branchTarget() called on instruction "
75 "that is not a PC-relative branch.");
80 StaticInst::branchTarget(ThreadContext
*tc
) const
82 panic("StaticInst::branchTarget() called on instruction "
83 "that is not an indirect branch.");
88 StaticInst::disassemble(Addr pc
, const SymbolTable
*symtab
) const
90 if (!cachedDisassembly
)
91 cachedDisassembly
= new string(generateDisassembly(pc
, symtab
));
93 return *cachedDisassembly
;
97 StaticInst::printFlags(std::ostream
&outs
,
98 const std::string
&separator
) const
100 bool printed_a_flag
= false;
102 for (unsigned int flag
= IsNop
; flag
< Num_Flags
; flag
++) {
107 outs
<< FlagsStrings
[flag
];
108 printed_a_flag
= true;