src/cpu/static_inst.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "cpu/static_inst.hh"
  30
  31 #include <iostream>
  32
  33 #include "sim/core.hh"
  34
  35 namespace {
  36
  37 static TheISA::ExtMachInst nopMachInst;
  38
  39 class NopStaticInst : public StaticInst
  40 {
  41   public:
  42     NopStaticInst() : StaticInst("gem5 nop", nopMachInst, No_OpClass)
  43     {}
  44
  45     Fault
  46     execute(ExecContext *xc, Trace::InstRecord *traceData) const override
  47     {
  48         return NoFault;
  49     }
  50
  51     void
  52     advancePC(TheISA::PCState &pcState) const override
  53     {
  54         pcState.advance();
  55     }
  56
  57     std::string
  58     generateDisassembly(Addr pc,
  59             const Loader::SymbolTable *symtab) const override
  60     {
  61         return mnemonic;
  62     }
  63
  64   private:
  65 };
  66
  67 }
  68
  69 StaticInstPtr StaticInst::nullStaticInstPtr;
  70 StaticInstPtr StaticInst::nopStaticInstPtr = new NopStaticInst;
  71
  72 using namespace std;
  73
  74 StaticInst::~StaticInst()
  75 {
  76     if (cachedDisassembly)
  77         delete cachedDisassembly;
  78 }
  79
  80 bool
  81 StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
  82                             TheISA::PCState &tgt) const
  83 {
  84     if (isDirectCtrl()) {
  85         tgt = branchTarget(pc);
  86         return true;
  87     }
  88
  89     if (isIndirectCtrl()) {
  90         tgt = branchTarget(tc);
  91         return true;
  92     }
  93
  94     return false;
  95 }
  96
  97 StaticInstPtr
  98 StaticInst::fetchMicroop(MicroPC upc) const
  99 {
 100     panic("StaticInst::fetchMicroop() called on instruction "
 101           "that is not microcoded.");
 102 }
 103
 104 TheISA::PCState
 105 StaticInst::branchTarget(const TheISA::PCState &pc) const
 106 {
 107     panic("StaticInst::branchTarget() called on instruction "
 108           "that is not a PC-relative branch.");
 109 }
 110
 111 TheISA::PCState
 112 StaticInst::branchTarget(ThreadContext *tc) const
 113 {
 114     panic("StaticInst::branchTarget() called on instruction "
 115           "that is not an indirect branch.");
 116 }
 117
 118 const string &
 119 StaticInst::disassemble(Addr pc, const Loader::SymbolTable *symtab) const
 120 {
 121     if (!cachedDisassembly)
 122         cachedDisassembly = new string(generateDisassembly(pc, symtab));
 123
 124     return *cachedDisassembly;
 125 }
 126
 127 void
 128 StaticInst::printFlags(std::ostream &outs,
 129     const std::string &separator) const
 130 {
 131     bool printed_a_flag = false;
 132
 133     for (unsigned int flag = IsNop; flag < Num_Flags; flag++) {
 134         if (flags[flag]) {
 135             if (printed_a_flag)
 136                 outs << separator;
 137
 138             outs << FlagsStrings[flag];
 139             printed_a_flag = true;
 140         }
 141     }
 142 }