src/cpu/static_inst.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #include <iostream>
  33
  34 #include "cpu/static_inst.hh"
  35 #include "sim/core.hh"
  36
  37 StaticInstPtr StaticInst::nullStaticInstPtr;
  38
  39 // Define the decode cache hash map.
  40 StaticInst::DecodeCache StaticInst::decodeCache;
  41 StaticInst::AddrDecodeCache StaticInst::addrDecodeCache;
  42 StaticInst::cacheElement StaticInst::recentDecodes[2];
  43
  44 using namespace std;
  45
  46 StaticInst::~StaticInst()
  47 {
  48     if (cachedDisassembly)
  49         delete cachedDisassembly;
  50 }
  51
  52 void
  53 StaticInst::dumpDecodeCacheStats()
  54 {
  55     cerr << "Decode hash table stats @ " << curTick() << ":" << endl;
  56     cerr << "\tnum entries = " << decodeCache.size() << endl;
  57     cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl;
  58     vector<int> hist(100, 0);
  59     int max_hist = 0;
  60     for (int i = 0; i < decodeCache.bucket_count(); ++i) {
  61         int count = decodeCache.elems_in_bucket(i);
  62         if (count > max_hist)
  63             max_hist = count;
  64         hist[count]++;
  65     }
  66     for (int i = 0; i <= max_hist; ++i) {
  67         cerr << "\tbuckets of size " << i << " = " << hist[i] << endl;
  68     }
  69 }
  70
  71 bool
  72 StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
  73                             TheISA::PCState &tgt) const
  74 {
  75     if (isDirectCtrl()) {
  76         tgt = branchTarget(pc);
  77         return true;
  78     }
  79
  80     if (isIndirectCtrl()) {
  81         tgt = branchTarget(tc);
  82         return true;
  83     }
  84
  85     return false;
  86 }
  87
  88 StaticInstPtr
  89 StaticInst::fetchMicroop(MicroPC upc) const
  90 {
  91     panic("StaticInst::fetchMicroop() called on instruction "
  92           "that is not microcoded.");
  93 }
  94
  95 TheISA::PCState
  96 StaticInst::branchTarget(const TheISA::PCState &pc) const
  97 {
  98     panic("StaticInst::branchTarget() called on instruction "
  99           "that is not a PC-relative branch.");
 100     M5_DUMMY_RETURN;
 101 }
 102
 103 TheISA::PCState
 104 StaticInst::branchTarget(ThreadContext *tc) const
 105 {
 106     panic("StaticInst::branchTarget() called on instruction "
 107           "that is not an indirect branch.");
 108     M5_DUMMY_RETURN;
 109 }
 110
 111 const string &
 112 StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const
 113 {
 114     if (!cachedDisassembly)
 115         cachedDisassembly = new string(generateDisassembly(pc, symtab));
 116
 117     return *cachedDisassembly;
 118 }