2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
34 #include "cpu/static_inst.hh"
35 #include "sim/core.hh"
37 StaticInstPtr
StaticInst::nullStaticInstPtr
;
39 // Define the decode cache hash map.
40 StaticInst::DecodeCache
StaticInst::decodeCache
;
41 StaticInst::AddrDecodeCache
StaticInst::addrDecodeCache
;
42 StaticInst::cacheElement
StaticInst::recentDecodes
[2];
46 StaticInst::~StaticInst()
48 if (cachedDisassembly
)
49 delete cachedDisassembly
;
53 StaticInst::dumpDecodeCacheStats()
55 cerr
<< "Decode hash table stats @ " << curTick() << ":" << endl
;
56 cerr
<< "\tnum entries = " << decodeCache
.size() << endl
;
57 cerr
<< "\tnum buckets = " << decodeCache
.bucket_count() << endl
;
58 vector
<int> hist(100, 0);
60 for (int i
= 0; i
< decodeCache
.bucket_count(); ++i
) {
61 int count
= decodeCache
.elems_in_bucket(i
);
66 for (int i
= 0; i
<= max_hist
; ++i
) {
67 cerr
<< "\tbuckets of size " << i
<< " = " << hist
[i
] << endl
;
72 StaticInst::hasBranchTarget(const TheISA::PCState
&pc
, ThreadContext
*tc
,
73 TheISA::PCState
&tgt
) const
76 tgt
= branchTarget(pc
);
80 if (isIndirectCtrl()) {
81 tgt
= branchTarget(tc
);
89 StaticInst::fetchMicroop(MicroPC upc
) const
91 panic("StaticInst::fetchMicroop() called on instruction "
92 "that is not microcoded.");
96 StaticInst::branchTarget(const TheISA::PCState
&pc
) const
98 panic("StaticInst::branchTarget() called on instruction "
99 "that is not a PC-relative branch.");
104 StaticInst::branchTarget(ThreadContext
*tc
) const
106 panic("StaticInst::branchTarget() called on instruction "
107 "that is not an indirect branch.");
112 StaticInst::disassemble(Addr pc
, const SymbolTable
*symtab
) const
114 if (!cachedDisassembly
)
115 cachedDisassembly
= new string(generateDisassembly(pc
, symtab
));
117 return *cachedDisassembly
;