src/cpu/static_inst.hh

   1 /*
   2  * Copyright (c) 2017, 2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __CPU_STATIC_INST_HH__
  43 #define __CPU_STATIC_INST_HH__
  44
  45 #include <bitset>
  46 #include <memory>
  47 #include <string>
  48
  49 #include "arch/registers.hh"
  50 #include "arch/types.hh"
  51 #include "base/logging.hh"
  52 #include "base/refcnt.hh"
  53 #include "base/types.hh"
  54 #include "config/the_isa.hh"
  55 #include "cpu/op_class.hh"
  56 #include "cpu/reg_class.hh"
  57 #include "cpu/static_inst_fwd.hh"
  58 #include "cpu/thread_context.hh"
  59 #include "enums/StaticInstFlags.hh"
  60 #include "sim/byteswap.hh"
  61
  62 // forward declarations
  63 class Packet;
  64
  65 class ExecContext;
  66
  67 namespace Loader
  68 {
  69 class SymbolTable;
  70 } // namespace Loader
  71
  72 namespace Trace
  73 {
  74 class InstRecord;
  75 } // namespace Trace
  76
  77 /**
  78  * Base, ISA-independent static instruction class.
  79  *
  80  * The main component of this class is the vector of flags and the
  81  * associated methods for reading them.  Any object that can rely
  82  * solely on these flags can process instructions without being
  83  * recompiled for multiple ISAs.
  84  */
  85 class StaticInst : public RefCounted, public StaticInstFlags
  86 {
  87   public:
  88     /// Binary extended machine instruction type.
  89     typedef TheISA::ExtMachInst ExtMachInst;
  90
  91     enum {
  92         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
  93         MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
  94     };
  95
  96     using RegIdArrayPtr = RegId (StaticInst:: *)[];
  97
  98   private:
  99     /// See srcRegIdx().
 100     RegId _srcRegIdx[MaxInstSrcRegs];
 101     RegIdArrayPtr _srcRegIdxPtr = nullptr;
 102
 103     /// See destRegIdx().
 104     RegId _destRegIdx[MaxInstDestRegs];
 105     RegIdArrayPtr _destRegIdxPtr = nullptr;
 106
 107   protected:
 108
 109     /// Flag values for this instruction.
 110     std::bitset<Num_Flags> flags;
 111
 112     /// See opClass().
 113     OpClass _opClass;
 114
 115     /// See numSrcRegs().
 116     int8_t _numSrcRegs;
 117
 118     /// See numDestRegs().
 119     int8_t _numDestRegs;
 120
 121     /// The following are used to track physical register usage
 122     /// for machines with separate int & FP reg files.
 123     //@{
 124     int8_t _numFPDestRegs;
 125     int8_t _numIntDestRegs;
 126     int8_t _numCCDestRegs;
 127     //@}
 128
 129     /** To use in architectures with vector register file. */
 130     /** @{ */
 131     int8_t _numVecDestRegs;
 132     int8_t _numVecElemDestRegs;
 133     int8_t _numVecPredDestRegs;
 134     /** @} */
 135
 136   public:
 137
 138     /// @name Register information.
 139     /// The sum of numFPDestRegs(), numIntDestRegs(), numVecDestRegs(),
 140     /// numVecElemDestRegs() and numVecPredDestRegs() equals numDestRegs().
 141     /// The former two functions are used to track physical register usage for
 142     /// machines with separate int & FP reg files, the next three are for
 143     /// machines with vector and predicate register files.
 144     //@{
 145     /// Number of source registers.
 146     int8_t numSrcRegs()  const { return _numSrcRegs; }
 147     /// Number of destination registers.
 148     int8_t numDestRegs() const { return _numDestRegs; }
 149     /// Number of floating-point destination regs.
 150     int8_t numFPDestRegs()  const { return _numFPDestRegs; }
 151     /// Number of integer destination regs.
 152     int8_t numIntDestRegs() const { return _numIntDestRegs; }
 153     /// Number of vector destination regs.
 154     int8_t numVecDestRegs() const { return _numVecDestRegs; }
 155     /// Number of vector element destination regs.
 156     int8_t numVecElemDestRegs() const { return _numVecElemDestRegs; }
 157     /// Number of predicate destination regs.
 158     int8_t numVecPredDestRegs() const { return _numVecPredDestRegs; }
 159     /// Number of coprocesor destination regs.
 160     int8_t numCCDestRegs() const { return _numCCDestRegs; }
 161     //@}
 162
 163     /// @name Flag accessors.
 164     /// These functions are used to access the values of the various
 165     /// instruction property flags.  See StaticInst::Flags for descriptions
 166     /// of the individual flags.
 167     //@{
 168
 169     bool isNop()          const { return flags[IsNop]; }
 170
 171     bool
 172     isMemRef() const
 173     {
 174         return flags[IsLoad] || flags[IsStore] || flags[IsAtomic];
 175     }
 176     bool isLoad()         const { return flags[IsLoad]; }
 177     bool isStore()        const { return flags[IsStore]; }
 178     bool isAtomic()       const { return flags[IsAtomic]; }
 179     bool isStoreConditional()     const { return flags[IsStoreConditional]; }
 180     bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
 181     bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
 182     bool isPrefetch()     const { return isInstPrefetch() ||
 183                                          isDataPrefetch(); }
 184
 185     bool isInteger()      const { return flags[IsInteger]; }
 186     bool isFloating()     const { return flags[IsFloating]; }
 187     bool isVector()       const { return flags[IsVector]; }
 188
 189     bool isControl()      const { return flags[IsControl]; }
 190     bool isCall()         const { return flags[IsCall]; }
 191     bool isReturn()       const { return flags[IsReturn]; }
 192     bool isDirectCtrl()   const { return flags[IsDirectControl]; }
 193     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
 194     bool isCondCtrl()     const { return flags[IsCondControl]; }
 195     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 196
 197     bool isSerializing()  const { return flags[IsSerializing] ||
 198                                       flags[IsSerializeBefore] ||
 199                                       flags[IsSerializeAfter]; }
 200     bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
 201     bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
 202     bool isSquashAfter() const { return flags[IsSquashAfter]; }
 203     bool
 204     isFullMemBarrier() const
 205     {
 206         return flags[IsReadBarrier] && flags[IsWriteBarrier];
 207     }
 208     bool isReadBarrier() const { return flags[IsReadBarrier]; }
 209     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
 210     bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
 211     bool isQuiesce() const { return flags[IsQuiesce]; }
 212     bool isUnverifiable() const { return flags[IsUnverifiable]; }
 213     bool isSyscall() const { return flags[IsSyscall]; }
 214     bool isMacroop() const { return flags[IsMacroop]; }
 215     bool isMicroop() const { return flags[IsMicroop]; }
 216     bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
 217     bool isLastMicroop() const { return flags[IsLastMicroop]; }
 218     bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
 219     // hardware transactional memory
 220     // HtmCmds must be identified as such in order
 221     // to provide them with necessary memory ordering semantics.
 222     bool isHtmStart() const { return flags[IsHtmStart]; }
 223     bool isHtmStop() const { return flags[IsHtmStop]; }
 224     bool isHtmCancel() const { return flags[IsHtmCancel]; }
 225
 226     bool
 227     isHtmCmd() const
 228     {
 229         return isHtmStart() || isHtmStop() || isHtmCancel();
 230     }
 231     //@}
 232
 233     void setFirstMicroop() { flags[IsFirstMicroop] = true; }
 234     void setLastMicroop() { flags[IsLastMicroop] = true; }
 235     void setDelayedCommit() { flags[IsDelayedCommit] = true; }
 236     void setFlag(Flags f) { flags[f] = true; }
 237
 238     /// Operation class.  Used to select appropriate function unit in issue.
 239     OpClass opClass()     const { return _opClass; }
 240
 241
 242     /// Return logical index (architectural reg num) of i'th destination reg.
 243     /// Only the entries from 0 through numDestRegs()-1 are valid.
 244     const RegId &destRegIdx(int i) const { return (this->*_destRegIdxPtr)[i]; }
 245
 246     void
 247     setDestRegIdx(int i, const RegId &val)
 248     {
 249         (this->*_destRegIdxPtr)[i] = val;
 250     }
 251
 252     /// Return logical index (architectural reg num) of i'th source reg.
 253     /// Only the entries from 0 through numSrcRegs()-1 are valid.
 254     const RegId &srcRegIdx(int i) const { return (this->*_srcRegIdxPtr)[i]; }
 255
 256     void
 257     setSrcRegIdx(int i, const RegId &val)
 258     {
 259         (this->*_srcRegIdxPtr)[i] = val;
 260     }
 261
 262     /// Pointer to a statically allocated "null" instruction object.
 263     static StaticInstPtr nullStaticInstPtr;
 264
 265     /// Pointer to a statically allocated generic "nop" instruction object.
 266     static StaticInstPtr nopStaticInstPtr;
 267
 268     /// The binary machine instruction.
 269     const ExtMachInst machInst;
 270
 271   protected:
 272
 273     /**
 274      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
 275      * methods.  Also useful to readily identify instructions from
 276      * within the debugger when #cachedDisassembly has not been
 277      * initialized.
 278      */
 279     const char *mnemonic;
 280
 281     /**
 282      * String representation of disassembly (lazily evaluated via
 283      * disassemble()).
 284      */
 285     mutable std::string *cachedDisassembly;
 286
 287     /**
 288      * Internal function to generate disassembly string.
 289      */
 290     virtual std::string
 291     generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const = 0;
 292
 293     /// Constructor.
 294     /// It's important to initialize everything here to a sane
 295     /// default, since the decoder generally only overrides
 296     /// the fields that are meaningful for the particular
 297     /// instruction.
 298     StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
 299         : _srcRegIdxPtr(
 300                 reinterpret_cast<RegIdArrayPtr>(&StaticInst::_srcRegIdx)),
 301           _destRegIdxPtr(
 302                 reinterpret_cast<RegIdArrayPtr>(&StaticInst::_destRegIdx)),
 303           _opClass(__opClass),
 304           _numSrcRegs(0), _numDestRegs(0), _numFPDestRegs(0),
 305           _numIntDestRegs(0), _numCCDestRegs(0), _numVecDestRegs(0),
 306           _numVecElemDestRegs(0), _numVecPredDestRegs(0), machInst(_machInst),
 307           mnemonic(_mnemonic), cachedDisassembly(0)
 308     { }
 309
 310   public:
 311     virtual ~StaticInst();
 312
 313     virtual Fault execute(ExecContext *xc,
 314                           Trace::InstRecord *traceData) const = 0;
 315
 316     virtual Fault initiateAcc(ExecContext *xc,
 317                               Trace::InstRecord *traceData) const
 318     {
 319         panic("initiateAcc not defined!");
 320     }
 321
 322     virtual Fault completeAcc(Packet *pkt, ExecContext *xc,
 323                               Trace::InstRecord *traceData) const
 324     {
 325         panic("completeAcc not defined!");
 326     }
 327
 328     virtual void advancePC(TheISA::PCState &pcState) const = 0;
 329
 330     /**
 331      * Return the microop that goes with a particular micropc. This should
 332      * only be defined/used in macroops which will contain microops
 333      */
 334     virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
 335
 336     /**
 337      * Return the target address for a PC-relative branch.
 338      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
 339      * should be true).
 340      */
 341     virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
 342
 343     /**
 344      * Return the target address for an indirect branch (jump).  The
 345      * register value is read from the supplied thread context, so
 346      * the result is valid only if the thread context is about to
 347      * execute the branch in question.  Invalid if not an indirect
 348      * branch (i.e. isIndirectCtrl() should be true).
 349      */
 350     virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
 351
 352     /**
 353      * Return true if the instruction is a control transfer, and if so,
 354      * return the target address as well.
 355      */
 356     bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
 357                          TheISA::PCState &tgt) const;
 358
 359     /**
 360      * Return string representation of disassembled instruction.
 361      * The default version of this function will call the internal
 362      * virtual generateDisassembly() function to get the string,
 363      * then cache it in #cachedDisassembly.  If the disassembly
 364      * should not be cached, this function should be overridden directly.
 365      */
 366     virtual const std::string &disassemble(Addr pc,
 367         const Loader::SymbolTable *symtab=nullptr) const;
 368
 369     /**
 370      * Print a separator separated list of this instruction's set flag
 371      * names on the given stream.
 372      */
 373     void printFlags(std::ostream &outs, const std::string &separator) const;
 374
 375     /// Return name of machine instruction
 376     std::string getName() { return mnemonic; }
 377
 378   protected:
 379     template<typename T>
 380     size_t
 381     simpleAsBytes(void *buf, size_t max_size, const T &t)
 382     {
 383         size_t size = sizeof(T);
 384         if (size <= max_size)
 385             *reinterpret_cast<T *>(buf) = htole<T>(t);
 386         return size;
 387     }
 388
 389   public:
 390     /**
 391      * Instruction classes can override this function to return a
 392      * a representation of themselves as a blob of bytes, generally assumed to
 393      * be that instructions ExtMachInst.
 394      *
 395      * buf is a buffer to hold the bytes.
 396      * max_size is the size allocated for that buffer by the caller.
 397      * The return value is how much data was actually put into the buffer,
 398      * zero if no data was put in the buffer, or the necessary size of the
 399      * buffer if there wasn't enough space.
 400      */
 401     virtual size_t asBytes(void *buf, size_t max_size) { return 0; }
 402 };
 403
 404 #endif // __CPU_STATIC_INST_HH__