src/cpu/static_inst.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #ifndef __CPU_STATIC_INST_HH__
  32 #define __CPU_STATIC_INST_HH__
  33
  34 #include <bitset>
  35 #include <string>
  36
  37 #include "arch/isa_traits.hh"
  38 #include "sim/faults.hh"
  39 #include "base/bitfield.hh"
  40 #include "base/hashmap.hh"
  41 #include "base/misc.hh"
  42 #include "base/refcnt.hh"
  43 #include "cpu/op_class.hh"
  44 #include "cpu/o3/dyn_inst.hh"
  45 #include "sim/faults.hh"
  46 #include "sim/host.hh"
  47
  48 // forward declarations
  49 struct AlphaSimpleImpl;
  50 struct OzoneImpl;
  51 struct SimpleImpl;
  52 class ThreadContext;
  53 class DynInst;
  54 class Packet;
  55
  56 template <class Impl>
  57 class OzoneDynInst;
  58
  59 class CheckerCPU;
  60 class FastCPU;
  61 class AtomicSimpleCPU;
  62 class TimingSimpleCPU;
  63 class InorderCPU;
  64 class SymbolTable;
  65
  66 namespace Trace {
  67     class InstRecord;
  68 }
  69
  70 /**
  71  * Base, ISA-independent static instruction class.
  72  *
  73  * The main component of this class is the vector of flags and the
  74  * associated methods for reading them.  Any object that can rely
  75  * solely on these flags can process instructions without being
  76  * recompiled for multiple ISAs.
  77  */
  78 class StaticInstBase : public RefCounted
  79 {
  80   protected:
  81
  82     /// Set of boolean static instruction properties.
  83     ///
  84     /// Notes:
  85     /// - The IsInteger and IsFloating flags are based on the class of
  86     /// registers accessed by the instruction.  Although most
  87     /// instructions will have exactly one of these two flags set, it
  88     /// is possible for an instruction to have neither (e.g., direct
  89     /// unconditional branches, memory barriers) or both (e.g., an
  90     /// FP/int conversion).
  91     /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
  92     /// will be set.
  93     /// - If IsControl is set, then exactly one of IsDirectControl or
  94     /// IsIndirect Control will be set, and exactly one of
  95     /// IsCondControl or IsUncondControl will be set.
  96     /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
  97     /// implemented as flags since in the current model there's no
  98     /// other way for instructions to inject behavior into the
  99     /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
 100     /// model we should be able to get rid of these flags and
 101     /// implement this behavior via the execute() methods.
 102     ///
 103     enum Flags {
 104         IsNop,          ///< Is a no-op (no effect at all).
 105
 106         IsInteger,      ///< References integer regs.
 107         IsFloating,     ///< References FP regs.
 108
 109         IsMemRef,       ///< References memory (load, store, or prefetch).
 110         IsLoad,         ///< Reads from memory (load or prefetch).
 111         IsStore,        ///< Writes to memory.
 112         IsStoreConditional,    ///< Store conditional instruction.
 113         IsInstPrefetch, ///< Instruction-cache prefetch.
 114         IsDataPrefetch, ///< Data-cache prefetch.
 115         IsCopy,         ///< Fast Cache block copy
 116
 117         IsControl,              ///< Control transfer instruction.
 118         IsDirectControl,        ///< PC relative control transfer.
 119         IsIndirectControl,      ///< Register indirect control transfer.
 120         IsCondControl,          ///< Conditional control transfer.
 121         IsUncondControl,        ///< Unconditional control transfer.
 122         IsCall,                 ///< Subroutine call.
 123         IsReturn,               ///< Subroutine return.
 124
 125         IsCondDelaySlot,///< Conditional Delay-Slot Instruction
 126
 127         IsThreadSync,   ///< Thread synchronization operation.
 128
 129         IsSerializing,  ///< Serializes pipeline: won't execute until all
 130                         /// older instructions have committed.
 131         IsSerializeBefore,
 132         IsSerializeAfter,
 133         IsMemBarrier,   ///< Is a memory barrier
 134         IsWriteBarrier, ///< Is a write barrier
 135
 136         IsNonSpeculative, ///< Should not be executed speculatively
 137         IsQuiesce,      ///< Is a quiesce instruction
 138
 139         IsIprAccess,    ///< Accesses IPRs
 140         IsUnverifiable, ///< Can't be verified by a checker
 141
 142         NumFlags
 143     };
 144
 145     /// Flag values for this instruction.
 146     std::bitset<NumFlags> flags;
 147
 148     /// See opClass().
 149     OpClass _opClass;
 150
 151     /// See numSrcRegs().
 152     int8_t _numSrcRegs;
 153
 154     /// See numDestRegs().
 155     int8_t _numDestRegs;
 156
 157     /// The following are used to track physical register usage
 158     /// for machines with separate int & FP reg files.
 159     //@{
 160     int8_t _numFPDestRegs;
 161     int8_t _numIntDestRegs;
 162     //@}
 163
 164     /// Constructor.
 165     /// It's important to initialize everything here to a sane
 166     /// default, since the decoder generally only overrides
 167     /// the fields that are meaningful for the particular
 168     /// instruction.
 169     StaticInstBase(OpClass __opClass)
 170         : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
 171           _numFPDestRegs(0), _numIntDestRegs(0)
 172     {
 173     }
 174
 175   public:
 176
 177     /// @name Register information.
 178     /// The sum of numFPDestRegs() and numIntDestRegs() equals
 179     /// numDestRegs().  The former two functions are used to track
 180     /// physical register usage for machines with separate int & FP
 181     /// reg files.
 182     //@{
 183     /// Number of source registers.
 184     int8_t numSrcRegs()  const { return _numSrcRegs; }
 185     /// Number of destination registers.
 186     int8_t numDestRegs() const { return _numDestRegs; }
 187     /// Number of floating-point destination regs.
 188     int8_t numFPDestRegs()  const { return _numFPDestRegs; }
 189     /// Number of integer destination regs.
 190     int8_t numIntDestRegs() const { return _numIntDestRegs; }
 191     //@}
 192
 193     /// @name Flag accessors.
 194     /// These functions are used to access the values of the various
 195     /// instruction property flags.  See StaticInstBase::Flags for descriptions
 196     /// of the individual flags.
 197     //@{
 198
 199     bool isNop()          const { return flags[IsNop]; }
 200
 201     bool isMemRef()       const { return flags[IsMemRef]; }
 202     bool isLoad()         const { return flags[IsLoad]; }
 203     bool isStore()        const { return flags[IsStore]; }
 204     bool isStoreConditional()     const { return flags[IsStoreConditional]; }
 205     bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
 206     bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
 207     bool isCopy()         const { return flags[IsCopy];}
 208
 209     bool isInteger()      const { return flags[IsInteger]; }
 210     bool isFloating()     const { return flags[IsFloating]; }
 211
 212     bool isControl()      const { return flags[IsControl]; }
 213     bool isCall()         const { return flags[IsCall]; }
 214     bool isReturn()       const { return flags[IsReturn]; }
 215     bool isDirectCtrl()   const { return flags[IsDirectControl]; }
 216     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
 217     bool isCondCtrl()     const { return flags[IsCondControl]; }
 218     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 219     bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
 220
 221     bool isThreadSync()   const { return flags[IsThreadSync]; }
 222     bool isSerializing()  const { return flags[IsSerializing] ||
 223                                       flags[IsSerializeBefore] ||
 224                                       flags[IsSerializeAfter]; }
 225     bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
 226     bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
 227     bool isMemBarrier()   const { return flags[IsMemBarrier]; }
 228     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
 229     bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
 230     bool isQuiesce() const { return flags[IsQuiesce]; }
 231     bool isIprAccess() const { return flags[IsIprAccess]; }
 232     bool isUnverifiable() const { return flags[IsUnverifiable]; }
 233     //@}
 234
 235     /// Operation class.  Used to select appropriate function unit in issue.
 236     OpClass opClass()     const { return _opClass; }
 237 };
 238
 239
 240 // forward declaration
 241 class StaticInstPtr;
 242
 243 /**
 244  * Generic yet ISA-dependent static instruction class.
 245  *
 246  * This class builds on StaticInstBase, defining fields and interfaces
 247  * that are generic across all ISAs but that differ in details
 248  * according to the specific ISA being used.
 249  */
 250 class StaticInst : public StaticInstBase
 251 {
 252   public:
 253
 254     /// Binary machine instruction type.
 255     typedef TheISA::MachInst MachInst;
 256     /// Binary extended machine instruction type.
 257     typedef TheISA::ExtMachInst ExtMachInst;
 258     /// Logical register index type.
 259     typedef TheISA::RegIndex RegIndex;
 260
 261     enum {
 262         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
 263         MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
 264     };
 265
 266
 267     /// Return logical index (architectural reg num) of i'th destination reg.
 268     /// Only the entries from 0 through numDestRegs()-1 are valid.
 269     RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
 270
 271     /// Return logical index (architectural reg num) of i'th source reg.
 272     /// Only the entries from 0 through numSrcRegs()-1 are valid.
 273     RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
 274
 275     /// Pointer to a statically allocated "null" instruction object.
 276     /// Used to give eaCompInst() and memAccInst() something to return
 277     /// when called on non-memory instructions.
 278     static StaticInstPtr nullStaticInstPtr;
 279
 280     /**
 281      * Memory references only: returns "fake" instruction representing
 282      * the effective address part of the memory operation.  Used to
 283      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 284      * just the EA computation.
 285      */
 286     virtual const
 287     StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
 288
 289     /**
 290      * Memory references only: returns "fake" instruction representing
 291      * the memory access part of the memory operation.  Used to
 292      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 293      * just the memory access (not the EA computation).
 294      */
 295     virtual const
 296     StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
 297
 298     /// The binary machine instruction.
 299     const ExtMachInst machInst;
 300
 301   protected:
 302
 303     /// See destRegIdx().
 304     RegIndex _destRegIdx[MaxInstDestRegs];
 305     /// See srcRegIdx().
 306     RegIndex _srcRegIdx[MaxInstSrcRegs];
 307
 308     /**
 309      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
 310      * methods.  Also useful to readily identify instructions from
 311      * within the debugger when #cachedDisassembly has not been
 312      * initialized.
 313      */
 314     const char *mnemonic;
 315
 316     /**
 317      * String representation of disassembly (lazily evaluated via
 318      * disassemble()).
 319      */
 320     mutable std::string *cachedDisassembly;
 321
 322     /**
 323      * Internal function to generate disassembly string.
 324      */
 325     virtual std::string
 326     generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 327
 328     /// Constructor.
 329     StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
 330         : StaticInstBase(__opClass),
 331           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
 332     {
 333     }
 334
 335   public:
 336
 337     virtual ~StaticInst()
 338     {
 339         if (cachedDisassembly)
 340             delete cachedDisassembly;
 341     }
 342
 343 /**
 344  * The execute() signatures are auto-generated by scons based on the
 345  * set of CPU models we are compiling in today.
 346  */
 347 #include "cpu/static_inst_exec_sigs.hh"
 348
 349     /**
 350      * Return the target address for a PC-relative branch.
 351      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
 352      * should be true).
 353      */
 354     virtual Addr branchTarget(Addr branchPC) const
 355     {
 356         panic("StaticInst::branchTarget() called on instruction "
 357               "that is not a PC-relative branch.");
 358     }
 359
 360     /**
 361      * Return the target address for an indirect branch (jump).  The
 362      * register value is read from the supplied thread context, so
 363      * the result is valid only if the thread context is about to
 364      * execute the branch in question.  Invalid if not an indirect
 365      * branch (i.e. isIndirectCtrl() should be true).
 366      */
 367     virtual Addr branchTarget(ThreadContext *tc) const
 368     {
 369         panic("StaticInst::branchTarget() called on instruction "
 370               "that is not an indirect branch.");
 371     }
 372
 373     /**
 374      * Return true if the instruction is a control transfer, and if so,
 375      * return the target address as well.
 376      */
 377     bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
 378
 379     /**
 380      * Return string representation of disassembled instruction.
 381      * The default version of this function will call the internal
 382      * virtual generateDisassembly() function to get the string,
 383      * then cache it in #cachedDisassembly.  If the disassembly
 384      * should not be cached, this function should be overridden directly.
 385      */
 386     virtual const std::string &disassemble(Addr pc,
 387                                            const SymbolTable *symtab = 0) const
 388     {
 389         if (!cachedDisassembly)
 390             cachedDisassembly =
 391                 new std::string(generateDisassembly(pc, symtab));
 392
 393         return *cachedDisassembly;
 394     }
 395
 396     /// Decoded instruction cache type.
 397     /// For now we're using a generic hash_map; this seems to work
 398     /// pretty well.
 399     typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
 400
 401     /// A cache of decoded instruction objects.
 402     static DecodeCache decodeCache;
 403
 404     /**
 405      * Dump some basic stats on the decode cache hash map.
 406      * Only gets called if DECODE_CACHE_HASH_STATS is defined.
 407      */
 408     static void dumpDecodeCacheStats();
 409
 410     /// Decode a machine instruction.
 411     /// @param mach_inst The binary instruction to decode.
 412     /// @retval A pointer to the corresponding StaticInst object.
 413     //This is defined as inline below.
 414     static StaticInstPtr decode(ExtMachInst mach_inst);
 415
 416     /// Return opcode of machine instruction
 417     uint32_t getOpcode() { return bits(machInst, 31, 26);}
 418
 419     /// Return name of machine instruction
 420     std::string getName() { return mnemonic; }
 421 };
 422
 423 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
 424
 425 /// Reference-counted pointer to a StaticInst object.
 426 /// This type should be used instead of "StaticInst *" so that
 427 /// StaticInst objects can be properly reference-counted.
 428 class StaticInstPtr : public RefCountingPtr<StaticInst>
 429 {
 430   public:
 431     /// Constructor.
 432     StaticInstPtr()
 433         : RefCountingPtr<StaticInst>()
 434     {
 435     }
 436
 437     /// Conversion from "StaticInst *".
 438     StaticInstPtr(StaticInst *p)
 439         : RefCountingPtr<StaticInst>(p)
 440     {
 441     }
 442
 443     /// Copy constructor.
 444     StaticInstPtr(const StaticInstPtr &r)
 445         : RefCountingPtr<StaticInst>(r)
 446     {
 447     }
 448
 449     /// Construct directly from machine instruction.
 450     /// Calls StaticInst::decode().
 451     StaticInstPtr(TheISA::ExtMachInst mach_inst)
 452         : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
 453     {
 454     }
 455
 456     /// Convert to pointer to StaticInstBase class.
 457     operator const StaticInstBasePtr()
 458     {
 459         return this->get();
 460     }
 461 };
 462
 463 inline StaticInstPtr
 464 StaticInst::decode(StaticInst::ExtMachInst mach_inst)
 465 {
 466 #ifdef DECODE_CACHE_HASH_STATS
 467     // Simple stats on decode hash_map.  Turns out the default
 468     // hash function is as good as anything I could come up with.
 469     const int dump_every_n = 10000000;
 470     static int decodes_til_dump = dump_every_n;
 471
 472     if (--decodes_til_dump == 0) {
 473         dumpDecodeCacheStats();
 474         decodes_til_dump = dump_every_n;
 475     }
 476 #endif
 477
 478     DecodeCache::iterator iter = decodeCache.find(mach_inst);
 479     if (iter != decodeCache.end()) {
 480         return iter->second;
 481     }
 482
 483     StaticInstPtr si = TheISA::decodeInst(mach_inst);
 484     decodeCache[mach_inst] = si;
 485     return si;
 486 }
 487
 488 #endif // __CPU_STATIC_INST_HH__