src/cpu/static_inst.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Steve Reinhardt
  30  */
  31
  32 #ifndef __CPU_STATIC_INST_HH__
  33 #define __CPU_STATIC_INST_HH__
  34
  35 #include <bitset>
  36 #include <string>
  37
  38 #include "arch/registers.hh"
  39 #include "arch/types.hh"
  40 #include "base/misc.hh"
  41 #include "base/refcnt.hh"
  42 #include "base/types.hh"
  43 #include "config/the_isa.hh"
  44 #include "cpu/op_class.hh"
  45 #include "cpu/static_inst_fwd.hh"
  46 #include "cpu/thread_context.hh"
  47 #include "sim/fault_fwd.hh"
  48
  49 // forward declarations
  50 class Packet;
  51
  52 struct O3CPUImpl;
  53 template <class Impl> class BaseO3DynInst;
  54 typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
  55 class InOrderDynInst;
  56
  57 class CheckerCPU;
  58 class AtomicSimpleCPU;
  59 class TimingSimpleCPU;
  60 class InorderCPU;
  61 class SymbolTable;
  62
  63 namespace Trace {
  64     class InstRecord;
  65 }
  66
  67 /**
  68  * Base, ISA-independent static instruction class.
  69  *
  70  * The main component of this class is the vector of flags and the
  71  * associated methods for reading them.  Any object that can rely
  72  * solely on these flags can process instructions without being
  73  * recompiled for multiple ISAs.
  74  */
  75 class StaticInst : public RefCounted
  76 {
  77   public:
  78     /// Binary extended machine instruction type.
  79     typedef TheISA::ExtMachInst ExtMachInst;
  80     /// Logical register index type.
  81     typedef TheISA::RegIndex RegIndex;
  82
  83     enum {
  84         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
  85         MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
  86     };
  87
  88     /// Set of boolean static instruction properties.
  89     ///
  90     /// Notes:
  91     /// - The IsInteger and IsFloating flags are based on the class of
  92     /// registers accessed by the instruction.  Although most
  93     /// instructions will have exactly one of these two flags set, it
  94     /// is possible for an instruction to have neither (e.g., direct
  95     /// unconditional branches, memory barriers) or both (e.g., an
  96     /// FP/int conversion).
  97     /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
  98     /// will be set.
  99     /// - If IsControl is set, then exactly one of IsDirectControl or
 100     /// IsIndirect Control will be set, and exactly one of
 101     /// IsCondControl or IsUncondControl will be set.
 102     /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
 103     /// implemented as flags since in the current model there's no
 104     /// other way for instructions to inject behavior into the
 105     /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
 106     /// model we should be able to get rid of these flags and
 107     /// implement this behavior via the execute() methods.
 108     ///
 109     enum Flags {
 110         IsNop,          ///< Is a no-op (no effect at all).
 111
 112         IsInteger,      ///< References integer regs.
 113         IsFloating,     ///< References FP regs.
 114         IsCC,           ///< References CC regs.
 115
 116         IsMemRef,       ///< References memory (load, store, or prefetch).
 117         IsLoad,         ///< Reads from memory (load or prefetch).
 118         IsStore,        ///< Writes to memory.
 119         IsStoreConditional,    ///< Store conditional instruction.
 120         IsIndexed,      ///< Accesses memory with an indexed address computation
 121         IsInstPrefetch, ///< Instruction-cache prefetch.
 122         IsDataPrefetch, ///< Data-cache prefetch.
 123
 124         IsControl,              ///< Control transfer instruction.
 125         IsDirectControl,        ///< PC relative control transfer.
 126         IsIndirectControl,      ///< Register indirect control transfer.
 127         IsCondControl,          ///< Conditional control transfer.
 128         IsUncondControl,        ///< Unconditional control transfer.
 129         IsCall,                 ///< Subroutine call.
 130         IsReturn,               ///< Subroutine return.
 131
 132         IsCondDelaySlot,///< Conditional Delay-Slot Instruction
 133
 134         IsThreadSync,   ///< Thread synchronization operation.
 135
 136         IsSerializing,  ///< Serializes pipeline: won't execute until all
 137                         /// older instructions have committed.
 138         IsSerializeBefore,
 139         IsSerializeAfter,
 140         IsMemBarrier,   ///< Is a memory barrier
 141         IsWriteBarrier, ///< Is a write barrier
 142         IsReadBarrier,  ///< Is a read barrier
 143         IsERET, /// <- Causes the IFU to stall (MIPS ISA)
 144
 145         IsNonSpeculative, ///< Should not be executed speculatively
 146         IsQuiesce,      ///< Is a quiesce instruction
 147
 148         IsIprAccess,    ///< Accesses IPRs
 149         IsUnverifiable, ///< Can't be verified by a checker
 150
 151         IsSyscall,      ///< Causes a system call to be emulated in syscall
 152                         /// emulation mode.
 153
 154         //Flags for microcode
 155         IsMacroop,      ///< Is a macroop containing microops
 156         IsMicroop,      ///< Is a microop
 157         IsDelayedCommit,        ///< This microop doesn't commit right away
 158         IsLastMicroop,  ///< This microop ends a microop sequence
 159         IsFirstMicroop, ///< This microop begins a microop sequence
 160         //This flag doesn't do anything yet
 161         IsMicroBranch,  ///< This microop branches within the microcode for a macroop
 162         IsDspOp,
 163         IsSquashAfter, ///< Squash all uncommitted state after executed
 164         NumFlags
 165     };
 166
 167   protected:
 168
 169     /// Flag values for this instruction.
 170     std::bitset<NumFlags> flags;
 171
 172     /// See opClass().
 173     OpClass _opClass;
 174
 175     /// See numSrcRegs().
 176     int8_t _numSrcRegs;
 177
 178     /// See numDestRegs().
 179     int8_t _numDestRegs;
 180
 181     /// The following are used to track physical register usage
 182     /// for machines with separate int & FP reg files.
 183     //@{
 184     int8_t _numFPDestRegs;
 185     int8_t _numIntDestRegs;
 186     int8_t _numCCDestRegs;
 187     //@}
 188
 189   public:
 190
 191     /// @name Register information.
 192     /// The sum of numFPDestRegs() and numIntDestRegs() equals
 193     /// numDestRegs().  The former two functions are used to track
 194     /// physical register usage for machines with separate int & FP
 195     /// reg files.
 196     //@{
 197     /// Number of source registers.
 198     int8_t numSrcRegs()  const { return _numSrcRegs; }
 199     /// Number of destination registers.
 200     int8_t numDestRegs() const { return _numDestRegs; }
 201     /// Number of floating-point destination regs.
 202     int8_t numFPDestRegs()  const { return _numFPDestRegs; }
 203     /// Number of integer destination regs.
 204     int8_t numIntDestRegs() const { return _numIntDestRegs; }
 205     //@}
 206
 207     /// @name Flag accessors.
 208     /// These functions are used to access the values of the various
 209     /// instruction property flags.  See StaticInst::Flags for descriptions
 210     /// of the individual flags.
 211     //@{
 212
 213     bool isNop()          const { return flags[IsNop]; }
 214
 215     bool isMemRef()       const { return flags[IsMemRef]; }
 216     bool isLoad()         const { return flags[IsLoad]; }
 217     bool isStore()        const { return flags[IsStore]; }
 218     bool isStoreConditional()     const { return flags[IsStoreConditional]; }
 219     bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
 220     bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
 221     bool isPrefetch()     const { return isInstPrefetch() ||
 222                                          isDataPrefetch(); }
 223
 224     bool isInteger()      const { return flags[IsInteger]; }
 225     bool isFloating()     const { return flags[IsFloating]; }
 226     bool isCC()           const { return flags[IsCC]; }
 227
 228     bool isControl()      const { return flags[IsControl]; }
 229     bool isCall()         const { return flags[IsCall]; }
 230     bool isReturn()       const { return flags[IsReturn]; }
 231     bool isDirectCtrl()   const { return flags[IsDirectControl]; }
 232     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
 233     bool isCondCtrl()     const { return flags[IsCondControl]; }
 234     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 235     bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
 236
 237     bool isThreadSync()   const { return flags[IsThreadSync]; }
 238     bool isSerializing()  const { return flags[IsSerializing] ||
 239                                       flags[IsSerializeBefore] ||
 240                                       flags[IsSerializeAfter]; }
 241     bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
 242     bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
 243     bool isSquashAfter() const { return flags[IsSquashAfter]; }
 244     bool isMemBarrier()   const { return flags[IsMemBarrier]; }
 245     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
 246     bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
 247     bool isQuiesce() const { return flags[IsQuiesce]; }
 248     bool isIprAccess() const { return flags[IsIprAccess]; }
 249     bool isUnverifiable() const { return flags[IsUnverifiable]; }
 250     bool isSyscall() const { return flags[IsSyscall]; }
 251     bool isMacroop() const { return flags[IsMacroop]; }
 252     bool isMicroop() const { return flags[IsMicroop]; }
 253     bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
 254     bool isLastMicroop() const { return flags[IsLastMicroop]; }
 255     bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
 256     //This flag doesn't do anything yet
 257     bool isMicroBranch() const { return flags[IsMicroBranch]; }
 258     //@}
 259
 260     void setLastMicroop() { flags[IsLastMicroop] = true; }
 261     void setDelayedCommit() { flags[IsDelayedCommit] = true; }
 262     void setFlag(Flags f) { flags[f] = true; }
 263
 264     /// Operation class.  Used to select appropriate function unit in issue.
 265     OpClass opClass()     const { return _opClass; }
 266
 267
 268     /// Return logical index (architectural reg num) of i'th destination reg.
 269     /// Only the entries from 0 through numDestRegs()-1 are valid.
 270     RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
 271
 272     /// Return logical index (architectural reg num) of i'th source reg.
 273     /// Only the entries from 0 through numSrcRegs()-1 are valid.
 274     RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
 275
 276     /// Pointer to a statically allocated "null" instruction object.
 277     /// Used to give eaCompInst() and memAccInst() something to return
 278     /// when called on non-memory instructions.
 279     static StaticInstPtr nullStaticInstPtr;
 280
 281     /**
 282      * Memory references only: returns "fake" instruction representing
 283      * the effective address part of the memory operation.  Used to
 284      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 285      * just the EA computation.
 286      */
 287     virtual const
 288     StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
 289
 290     /**
 291      * Memory references only: returns "fake" instruction representing
 292      * the memory access part of the memory operation.  Used to
 293      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 294      * just the memory access (not the EA computation).
 295      */
 296     virtual const
 297     StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
 298
 299     /// The binary machine instruction.
 300     const ExtMachInst machInst;
 301
 302   protected:
 303
 304     /// See destRegIdx().
 305     RegIndex _destRegIdx[MaxInstDestRegs];
 306     /// See srcRegIdx().
 307     RegIndex _srcRegIdx[MaxInstSrcRegs];
 308
 309     /**
 310      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
 311      * methods.  Also useful to readily identify instructions from
 312      * within the debugger when #cachedDisassembly has not been
 313      * initialized.
 314      */
 315     const char *mnemonic;
 316
 317     /**
 318      * String representation of disassembly (lazily evaluated via
 319      * disassemble()).
 320      */
 321     mutable std::string *cachedDisassembly;
 322
 323     /**
 324      * Internal function to generate disassembly string.
 325      */
 326     virtual std::string
 327     generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 328
 329     /// Constructor.
 330     /// It's important to initialize everything here to a sane
 331     /// default, since the decoder generally only overrides
 332     /// the fields that are meaningful for the particular
 333     /// instruction.
 334     StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
 335         : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
 336           _numFPDestRegs(0), _numIntDestRegs(0),
 337           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
 338     { }
 339
 340   public:
 341     virtual ~StaticInst();
 342
 343 /**
 344  * The execute() signatures are auto-generated by scons based on the
 345  * set of CPU models we are compiling in today.
 346  */
 347 #include "cpu/static_inst_exec_sigs.hh"
 348
 349     virtual void advancePC(TheISA::PCState &pcState) const = 0;
 350
 351     /**
 352      * Return the microop that goes with a particular micropc. This should
 353      * only be defined/used in macroops which will contain microops
 354      */
 355     virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
 356
 357     /**
 358      * Return the target address for a PC-relative branch.
 359      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
 360      * should be true).
 361      */
 362     virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
 363
 364     /**
 365      * Return the target address for an indirect branch (jump).  The
 366      * register value is read from the supplied thread context, so
 367      * the result is valid only if the thread context is about to
 368      * execute the branch in question.  Invalid if not an indirect
 369      * branch (i.e. isIndirectCtrl() should be true).
 370      */
 371     virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
 372
 373     /**
 374      * Return true if the instruction is a control transfer, and if so,
 375      * return the target address as well.
 376      */
 377     bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
 378                          TheISA::PCState &tgt) const;
 379
 380     /**
 381      * Return string representation of disassembled instruction.
 382      * The default version of this function will call the internal
 383      * virtual generateDisassembly() function to get the string,
 384      * then cache it in #cachedDisassembly.  If the disassembly
 385      * should not be cached, this function should be overridden directly.
 386      */
 387     virtual const std::string &disassemble(Addr pc,
 388         const SymbolTable *symtab = 0) const;
 389
 390     /// Return name of machine instruction
 391     std::string getName() { return mnemonic; }
 392 };
 393
 394 #endif // __CPU_STATIC_INST_HH__