src/cpu/static_inst.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #ifndef __CPU_STATIC_INST_HH__
  32 #define __CPU_STATIC_INST_HH__
  33
  34 #include <bitset>
  35 #include <string>
  36
  37 #include "arch/isa_traits.hh"
  38 #include "arch/utility.hh"
  39 #include "sim/faults.hh"
  40 #include "base/bitfield.hh"
  41 #include "base/hashmap.hh"
  42 #include "base/misc.hh"
  43 #include "base/refcnt.hh"
  44 #include "cpu/op_class.hh"
  45 #include "cpu/o3/dyn_inst.hh"
  46 #include "sim/faults.hh"
  47 #include "sim/host.hh"
  48
  49 // forward declarations
  50 struct AlphaSimpleImpl;
  51 struct OzoneImpl;
  52 struct SimpleImpl;
  53 class ThreadContext;
  54 class DynInst;
  55 class Packet;
  56
  57 template <class Impl>
  58 class OzoneDynInst;
  59
  60 class CheckerCPU;
  61 class FastCPU;
  62 class AtomicSimpleCPU;
  63 class TimingSimpleCPU;
  64 class InorderCPU;
  65 class SymbolTable;
  66 class AddrDecodePage;
  67
  68 namespace Trace {
  69     class InstRecord;
  70 }
  71
  72 typedef uint32_t MicroPC;
  73
  74 /**
  75  * Base, ISA-independent static instruction class.
  76  *
  77  * The main component of this class is the vector of flags and the
  78  * associated methods for reading them.  Any object that can rely
  79  * solely on these flags can process instructions without being
  80  * recompiled for multiple ISAs.
  81  */
  82 class StaticInstBase : public RefCounted
  83 {
  84   protected:
  85
  86     /// Set of boolean static instruction properties.
  87     ///
  88     /// Notes:
  89     /// - The IsInteger and IsFloating flags are based on the class of
  90     /// registers accessed by the instruction.  Although most
  91     /// instructions will have exactly one of these two flags set, it
  92     /// is possible for an instruction to have neither (e.g., direct
  93     /// unconditional branches, memory barriers) or both (e.g., an
  94     /// FP/int conversion).
  95     /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
  96     /// will be set.
  97     /// - If IsControl is set, then exactly one of IsDirectControl or
  98     /// IsIndirect Control will be set, and exactly one of
  99     /// IsCondControl or IsUncondControl will be set.
 100     /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
 101     /// implemented as flags since in the current model there's no
 102     /// other way for instructions to inject behavior into the
 103     /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
 104     /// model we should be able to get rid of these flags and
 105     /// implement this behavior via the execute() methods.
 106     ///
 107     enum Flags {
 108         IsNop,          ///< Is a no-op (no effect at all).
 109
 110         IsInteger,      ///< References integer regs.
 111         IsFloating,     ///< References FP regs.
 112
 113         IsMemRef,       ///< References memory (load, store, or prefetch).
 114         IsLoad,         ///< Reads from memory (load or prefetch).
 115         IsStore,        ///< Writes to memory.
 116         IsStoreConditional,    ///< Store conditional instruction.
 117         IsInstPrefetch, ///< Instruction-cache prefetch.
 118         IsDataPrefetch, ///< Data-cache prefetch.
 119         IsCopy,         ///< Fast Cache block copy
 120
 121         IsControl,              ///< Control transfer instruction.
 122         IsDirectControl,        ///< PC relative control transfer.
 123         IsIndirectControl,      ///< Register indirect control transfer.
 124         IsCondControl,          ///< Conditional control transfer.
 125         IsUncondControl,        ///< Unconditional control transfer.
 126         IsCall,                 ///< Subroutine call.
 127         IsReturn,               ///< Subroutine return.
 128
 129         IsCondDelaySlot,///< Conditional Delay-Slot Instruction
 130
 131         IsThreadSync,   ///< Thread synchronization operation.
 132
 133         IsSerializing,  ///< Serializes pipeline: won't execute until all
 134                         /// older instructions have committed.
 135         IsSerializeBefore,
 136         IsSerializeAfter,
 137         IsMemBarrier,   ///< Is a memory barrier
 138         IsWriteBarrier, ///< Is a write barrier
 139
 140         IsNonSpeculative, ///< Should not be executed speculatively
 141         IsQuiesce,      ///< Is a quiesce instruction
 142
 143         IsIprAccess,    ///< Accesses IPRs
 144         IsUnverifiable, ///< Can't be verified by a checker
 145
 146         //Flags for microcode
 147         IsMacroop,      ///< Is a macroop containing microops
 148         IsMicroop,      ///< Is a microop
 149         IsDelayedCommit,        ///< This microop doesn't commit right away
 150         IsLastMicroop,  ///< This microop ends a microop sequence
 151         IsFirstMicroop, ///< This microop begins a microop sequence
 152         //This flag doesn't do anything yet
 153         IsMicroBranch,  ///< This microop branches within the microcode for a macroop
 154
 155         NumFlags
 156     };
 157
 158     /// Flag values for this instruction.
 159     std::bitset<NumFlags> flags;
 160
 161     /// See opClass().
 162     OpClass _opClass;
 163
 164     /// See numSrcRegs().
 165     int8_t _numSrcRegs;
 166
 167     /// See numDestRegs().
 168     int8_t _numDestRegs;
 169
 170     /// The following are used to track physical register usage
 171     /// for machines with separate int & FP reg files.
 172     //@{
 173     int8_t _numFPDestRegs;
 174     int8_t _numIntDestRegs;
 175     //@}
 176
 177     /// Constructor.
 178     /// It's important to initialize everything here to a sane
 179     /// default, since the decoder generally only overrides
 180     /// the fields that are meaningful for the particular
 181     /// instruction.
 182     StaticInstBase(OpClass __opClass)
 183         : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
 184           _numFPDestRegs(0), _numIntDestRegs(0)
 185     {
 186     }
 187
 188   public:
 189
 190     /// @name Register information.
 191     /// The sum of numFPDestRegs() and numIntDestRegs() equals
 192     /// numDestRegs().  The former two functions are used to track
 193     /// physical register usage for machines with separate int & FP
 194     /// reg files.
 195     //@{
 196     /// Number of source registers.
 197     int8_t numSrcRegs()  const { return _numSrcRegs; }
 198     /// Number of destination registers.
 199     int8_t numDestRegs() const { return _numDestRegs; }
 200     /// Number of floating-point destination regs.
 201     int8_t numFPDestRegs()  const { return _numFPDestRegs; }
 202     /// Number of integer destination regs.
 203     int8_t numIntDestRegs() const { return _numIntDestRegs; }
 204     //@}
 205
 206     /// @name Flag accessors.
 207     /// These functions are used to access the values of the various
 208     /// instruction property flags.  See StaticInstBase::Flags for descriptions
 209     /// of the individual flags.
 210     //@{
 211
 212     bool isNop()          const { return flags[IsNop]; }
 213
 214     bool isMemRef()       const { return flags[IsMemRef]; }
 215     bool isLoad()         const { return flags[IsLoad]; }
 216     bool isStore()        const { return flags[IsStore]; }
 217     bool isStoreConditional()     const { return flags[IsStoreConditional]; }
 218     bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
 219     bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
 220     bool isCopy()         const { return flags[IsCopy];}
 221
 222     bool isInteger()      const { return flags[IsInteger]; }
 223     bool isFloating()     const { return flags[IsFloating]; }
 224
 225     bool isControl()      const { return flags[IsControl]; }
 226     bool isCall()         const { return flags[IsCall]; }
 227     bool isReturn()       const { return flags[IsReturn]; }
 228     bool isDirectCtrl()   const { return flags[IsDirectControl]; }
 229     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
 230     bool isCondCtrl()     const { return flags[IsCondControl]; }
 231     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 232     bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
 233
 234     bool isThreadSync()   const { return flags[IsThreadSync]; }
 235     bool isSerializing()  const { return flags[IsSerializing] ||
 236                                       flags[IsSerializeBefore] ||
 237                                       flags[IsSerializeAfter]; }
 238     bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
 239     bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
 240     bool isMemBarrier()   const { return flags[IsMemBarrier]; }
 241     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
 242     bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
 243     bool isQuiesce() const { return flags[IsQuiesce]; }
 244     bool isIprAccess() const { return flags[IsIprAccess]; }
 245     bool isUnverifiable() const { return flags[IsUnverifiable]; }
 246     bool isMacroop() const { return flags[IsMacroop]; }
 247     bool isMicroop() const { return flags[IsMicroop]; }
 248     bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
 249     bool isLastMicroop() const { return flags[IsLastMicroop]; }
 250     bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
 251     //This flag doesn't do anything yet
 252     bool isMicroBranch() const { return flags[IsMicroBranch]; }
 253     //@}
 254
 255     /// Operation class.  Used to select appropriate function unit in issue.
 256     OpClass opClass()     const { return _opClass; }
 257 };
 258
 259
 260 // forward declaration
 261 class StaticInstPtr;
 262
 263 /**
 264  * Generic yet ISA-dependent static instruction class.
 265  *
 266  * This class builds on StaticInstBase, defining fields and interfaces
 267  * that are generic across all ISAs but that differ in details
 268  * according to the specific ISA being used.
 269  */
 270 class StaticInst : public StaticInstBase
 271 {
 272   public:
 273
 274     /// Binary machine instruction type.
 275     typedef TheISA::MachInst MachInst;
 276     /// Binary extended machine instruction type.
 277     typedef TheISA::ExtMachInst ExtMachInst;
 278     /// Logical register index type.
 279     typedef TheISA::RegIndex RegIndex;
 280
 281     enum {
 282         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
 283         MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
 284     };
 285
 286
 287     /// Return logical index (architectural reg num) of i'th destination reg.
 288     /// Only the entries from 0 through numDestRegs()-1 are valid.
 289     RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
 290
 291     /// Return logical index (architectural reg num) of i'th source reg.
 292     /// Only the entries from 0 through numSrcRegs()-1 are valid.
 293     RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
 294
 295     /// Pointer to a statically allocated "null" instruction object.
 296     /// Used to give eaCompInst() and memAccInst() something to return
 297     /// when called on non-memory instructions.
 298     static StaticInstPtr nullStaticInstPtr;
 299
 300     /**
 301      * Memory references only: returns "fake" instruction representing
 302      * the effective address part of the memory operation.  Used to
 303      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 304      * just the EA computation.
 305      */
 306     virtual const
 307     StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
 308
 309     /**
 310      * Memory references only: returns "fake" instruction representing
 311      * the memory access part of the memory operation.  Used to
 312      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 313      * just the memory access (not the EA computation).
 314      */
 315     virtual const
 316     StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
 317
 318     /// The binary machine instruction.
 319     const ExtMachInst machInst;
 320
 321   protected:
 322
 323     /// See destRegIdx().
 324     RegIndex _destRegIdx[MaxInstDestRegs];
 325     /// See srcRegIdx().
 326     RegIndex _srcRegIdx[MaxInstSrcRegs];
 327
 328     /**
 329      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
 330      * methods.  Also useful to readily identify instructions from
 331      * within the debugger when #cachedDisassembly has not been
 332      * initialized.
 333      */
 334     const char *mnemonic;
 335
 336     /**
 337      * String representation of disassembly (lazily evaluated via
 338      * disassemble()).
 339      */
 340     mutable std::string *cachedDisassembly;
 341
 342     /**
 343      * Internal function to generate disassembly string.
 344      */
 345     virtual std::string
 346     generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 347
 348     /// Constructor.
 349     StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
 350         : StaticInstBase(__opClass),
 351           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
 352     {
 353         memset(&recentDecodes, 0, 2 * sizeof(cacheElement));
 354     }
 355
 356   public:
 357
 358     virtual ~StaticInst()
 359     {
 360         if (cachedDisassembly)
 361             delete cachedDisassembly;
 362     }
 363
 364 /**
 365  * The execute() signatures are auto-generated by scons based on the
 366  * set of CPU models we are compiling in today.
 367  */
 368 #include "cpu/static_inst_exec_sigs.hh"
 369
 370     /**
 371      * Return the microop that goes with a particular micropc. This should
 372      * only be defined/used in macroops which will contain microops
 373      */
 374     virtual StaticInstPtr fetchMicroop(MicroPC micropc);
 375
 376     /**
 377      * Return the target address for a PC-relative branch.
 378      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
 379      * should be true).
 380      */
 381     virtual Addr branchTarget(Addr branchPC) const
 382     {
 383         panic("StaticInst::branchTarget() called on instruction "
 384               "that is not a PC-relative branch.");
 385         M5_DUMMY_RETURN
 386     }
 387
 388     /**
 389      * Return the target address for an indirect branch (jump).  The
 390      * register value is read from the supplied thread context, so
 391      * the result is valid only if the thread context is about to
 392      * execute the branch in question.  Invalid if not an indirect
 393      * branch (i.e. isIndirectCtrl() should be true).
 394      */
 395     virtual Addr branchTarget(ThreadContext *tc) const
 396     {
 397         panic("StaticInst::branchTarget() called on instruction "
 398               "that is not an indirect branch.");
 399     }
 400         M5_DUMMY_RETURN
 401
 402     /**
 403      * Return true if the instruction is a control transfer, and if so,
 404      * return the target address as well.
 405      */
 406     bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
 407
 408     /**
 409      * Return string representation of disassembled instruction.
 410      * The default version of this function will call the internal
 411      * virtual generateDisassembly() function to get the string,
 412      * then cache it in #cachedDisassembly.  If the disassembly
 413      * should not be cached, this function should be overridden directly.
 414      */
 415     virtual const std::string &disassemble(Addr pc,
 416                                            const SymbolTable *symtab = 0) const
 417     {
 418         if (!cachedDisassembly)
 419             cachedDisassembly =
 420                 new std::string(generateDisassembly(pc, symtab));
 421
 422         return *cachedDisassembly;
 423     }
 424
 425     /// Decoded instruction cache type.
 426     /// For now we're using a generic hash_map; this seems to work
 427     /// pretty well.
 428     typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
 429
 430     /// A cache of decoded instruction objects.
 431     static DecodeCache decodeCache;
 432
 433     /**
 434      * Dump some basic stats on the decode cache hash map.
 435      * Only gets called if DECODE_CACHE_HASH_STATS is defined.
 436      */
 437     static void dumpDecodeCacheStats();
 438
 439     /// Decode a machine instruction.
 440     /// @param mach_inst The binary instruction to decode.
 441     /// @retval A pointer to the corresponding StaticInst object.
 442     //This is defined as inlined below.
 443     static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
 444
 445     /// Return name of machine instruction
 446     std::string getName() { return mnemonic; }
 447
 448     /// Decoded instruction cache type, for address decoding.
 449     /// A generic hash_map is used.
 450     typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache;
 451
 452     /// A cache of decoded instruction objects from addresses.
 453     static AddrDecodeCache addrDecodeCache;
 454
 455     struct cacheElement {
 456         Addr page_addr;
 457         AddrDecodePage *decodePage;
 458     } ;
 459
 460     /// An array of recently decoded instructions.
 461     // might not use an array if there is only two elements
 462     static struct cacheElement recentDecodes[2];
 463
 464     /// Updates the recently decoded instructions entries
 465     /// @param page_addr The page address recently used.
 466     /// @param decodePage Pointer to decoding page containing the decoded
 467     ///                   instruction.
 468     static inline void
 469     updateCache(Addr page_addr, AddrDecodePage *decodePage)
 470     {
 471         recentDecodes[1].page_addr = recentDecodes[0].page_addr;
 472         recentDecodes[1].decodePage = recentDecodes[0].decodePage;
 473         recentDecodes[0].page_addr = page_addr;
 474         recentDecodes[0].decodePage = decodePage;
 475     }
 476
 477     /// Searches the decoded instruction cache for instruction decoding.
 478     /// If it is not found, then we decode the instruction.
 479     /// Otherwise, we get the instruction from the cache and move it into
 480     /// the address-to-instruction decoding page.
 481     /// @param mach_inst The binary instruction to decode.
 482     /// @param addr The address that contained the binary instruction.
 483     /// @param decodePage Pointer to decoding page containing the instruction.
 484     /// @retval A pointer to the corresponding StaticInst object.
 485     //This is defined as inlined below.
 486     static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr,
 487                                      AddrDecodePage * decodePage);
 488 };
 489
 490 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
 491
 492 /// Reference-counted pointer to a StaticInst object.
 493 /// This type should be used instead of "StaticInst *" so that
 494 /// StaticInst objects can be properly reference-counted.
 495 class StaticInstPtr : public RefCountingPtr<StaticInst>
 496 {
 497   public:
 498     /// Constructor.
 499     StaticInstPtr()
 500         : RefCountingPtr<StaticInst>()
 501     {
 502     }
 503
 504     /// Conversion from "StaticInst *".
 505     StaticInstPtr(StaticInst *p)
 506         : RefCountingPtr<StaticInst>(p)
 507     {
 508     }
 509
 510     /// Copy constructor.
 511     StaticInstPtr(const StaticInstPtr &r)
 512         : RefCountingPtr<StaticInst>(r)
 513     {
 514     }
 515
 516     /// Construct directly from machine instruction.
 517     /// Calls StaticInst::decode().
 518     explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr)
 519         : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr))
 520     {
 521     }
 522
 523     /// Convert to pointer to StaticInstBase class.
 524     operator const StaticInstBasePtr()
 525     {
 526         return this->get();
 527     }
 528 };
 529
 530 /// A page of a list of decoded instructions from an address.
 531 class AddrDecodePage
 532 {
 533   typedef TheISA::ExtMachInst ExtMachInst;
 534   protected:
 535     StaticInstPtr instructions[TheISA::PageBytes];
 536     bool valid[TheISA::PageBytes];
 537     Addr lowerMask;
 538
 539   public:
 540     /// Constructor
 541     AddrDecodePage() {
 542         lowerMask = TheISA::PageBytes - 1;
 543         memset(valid, 0, TheISA::PageBytes);
 544     }
 545
 546     /// Checks if the instruction is already decoded and the machine
 547     /// instruction in the cache matches the current machine instruction
 548     /// related to the address
 549     /// @param mach_inst The binary instruction to check
 550     /// @param addr The address containing the instruction
 551     inline bool decoded(ExtMachInst mach_inst, Addr addr)
 552     {
 553         return (valid[addr & lowerMask] &&
 554                 (instructions[addr & lowerMask]->machInst == mach_inst));
 555     }
 556
 557     /// Returns the instruction object. decoded should be called first
 558     /// to check if the instruction is valid.
 559     /// @param addr The address of the instruction.
 560     /// @retval A pointer to the corresponding StaticInst object.
 561     inline StaticInstPtr getInst(Addr addr)
 562     {   return instructions[addr & lowerMask]; }
 563
 564     /// Inserts a pointer to a StaticInst object into the list of decoded
 565     /// instructions on the page.
 566     /// @param addr The address of the instruction.
 567     /// @param si A pointer to the corresponding StaticInst object.
 568     inline void insert(Addr addr, StaticInstPtr &si)
 569     {
 570         instructions[addr & lowerMask] = si;
 571         valid[addr & lowerMask] = true;
 572     }
 573
 574 };
 575
 576
 577 inline StaticInstPtr
 578 StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
 579 {
 580 #ifdef DECODE_CACHE_HASH_STATS
 581     // Simple stats on decode hash_map.  Turns out the default
 582     // hash function is as good as anything I could come up with.
 583     const int dump_every_n = 10000000;
 584     static int decodes_til_dump = dump_every_n;
 585
 586     if (--decodes_til_dump == 0) {
 587         dumpDecodeCacheStats();
 588         decodes_til_dump = dump_every_n;
 589     }
 590 #endif
 591
 592     Addr page_addr = addr & ~(TheISA::PageBytes - 1);
 593
 594     // checks recently decoded addresses
 595     if (recentDecodes[0].decodePage &&
 596         page_addr == recentDecodes[0].page_addr) {
 597         if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
 598             return recentDecodes[0].decodePage->getInst(addr);
 599
 600         return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
 601     }
 602
 603     if (recentDecodes[1].decodePage &&
 604         page_addr == recentDecodes[1].page_addr) {
 605         if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
 606             return recentDecodes[1].decodePage->getInst(addr);
 607
 608         return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
 609     }
 610
 611     // searches the page containing the address to decode
 612     AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr);
 613     if (iter != addrDecodeCache.end()) {
 614         updateCache(page_addr, iter->second);
 615         if (iter->second->decoded(mach_inst, addr))
 616             return iter->second->getInst(addr);
 617
 618         return searchCache(mach_inst, addr, iter->second);
 619     }
 620
 621     // creates a new object for a page of decoded instructions
 622     AddrDecodePage * decodePage = new AddrDecodePage;
 623     addrDecodeCache[page_addr] = decodePage;
 624     updateCache(page_addr, decodePage);
 625     return searchCache(mach_inst, addr, decodePage);
 626 }
 627
 628 inline StaticInstPtr
 629 StaticInst::searchCache(ExtMachInst mach_inst, Addr addr,
 630                         AddrDecodePage * decodePage)
 631 {
 632     DecodeCache::iterator iter = decodeCache.find(mach_inst);
 633     if (iter != decodeCache.end()) {
 634         decodePage->insert(addr, iter->second);
 635         return iter->second;
 636     }
 637
 638     StaticInstPtr si = TheISA::decodeInst(mach_inst);
 639     decodePage->insert(addr, si);
 640     decodeCache[mach_inst] = si;
 641     return si;
 642 }
 643
 644 #endif // __CPU_STATIC_INST_HH__