2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #ifndef __CPU_STATIC_INST_HH__
32 #define __CPU_STATIC_INST_HH__
37 #include "arch/isa_traits.hh"
38 #include "arch/utility.hh"
39 #include "base/bitfield.hh"
40 #include "base/hashmap.hh"
41 #include "base/misc.hh"
42 #include "base/refcnt.hh"
43 #include "base/types.hh"
44 #include "cpu/op_class.hh"
45 #include "sim/faults.hh"
46 #include "sim/faults.hh"
48 // forward declarations
49 struct AlphaSimpleImpl;
57 template <class Impl> class BaseO3DynInst;
58 typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
59 template <class Impl> class OzoneDynInst;
64 class AtomicSimpleCPU;
65 class TimingSimpleCPU;
74 typedef uint16_t MicroPC;
76 static const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1);
79 romMicroPC(MicroPC upc)
81 return upc | MicroPCRomBit;
85 normalMicroPC(MicroPC upc)
87 return upc & ~MicroPCRomBit;
91 isRomMicroPC(MicroPC upc)
93 return MicroPCRomBit & upc;
97 * Base, ISA-independent static instruction class.
99 * The main component of this class is the vector of flags and the
100 * associated methods for reading them. Any object that can rely
101 * solely on these flags can process instructions without being
102 * recompiled for multiple ISAs.
104 class StaticInstBase : public RefCounted
108 /// Set of boolean static instruction properties.
111 /// - The IsInteger and IsFloating flags are based on the class of
112 /// registers accessed by the instruction. Although most
113 /// instructions will have exactly one of these two flags set, it
114 /// is possible for an instruction to have neither (e.g., direct
115 /// unconditional branches, memory barriers) or both (e.g., an
116 /// FP/int conversion).
117 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
119 /// - If IsControl is set, then exactly one of IsDirectControl or
120 /// IsIndirect Control will be set, and exactly one of
121 /// IsCondControl or IsUncondControl will be set.
122 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
123 /// implemented as flags since in the current model there's no
124 /// other way for instructions to inject behavior into the
125 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
126 /// model we should be able to get rid of these flags and
127 /// implement this behavior via the execute() methods.
130 IsNop, ///< Is a no-op (no effect at all).
132 IsInteger, ///< References integer regs.
133 IsFloating, ///< References FP regs.
135 IsMemRef, ///< References memory (load, store, or prefetch).
136 IsLoad, ///< Reads from memory (load or prefetch).
137 IsStore, ///< Writes to memory.
138 IsStoreConditional, ///< Store conditional instruction.
139 IsIndexed, ///< Accesses memory with an indexed address computation
140 IsInstPrefetch, ///< Instruction-cache prefetch.
141 IsDataPrefetch, ///< Data-cache prefetch.
142 IsCopy, ///< Fast Cache block copy
144 IsControl, ///< Control transfer instruction.
145 IsDirectControl, ///< PC relative control transfer.
146 IsIndirectControl, ///< Register indirect control transfer.
147 IsCondControl, ///< Conditional control transfer.
148 IsUncondControl, ///< Unconditional control transfer.
149 IsCall, ///< Subroutine call.
150 IsReturn, ///< Subroutine return.
152 IsCondDelaySlot,///< Conditional Delay-Slot Instruction
154 IsThreadSync, ///< Thread synchronization operation.
156 IsSerializing, ///< Serializes pipeline: won't execute until all
157 /// older instructions have committed.
160 IsMemBarrier, ///< Is a memory barrier
161 IsWriteBarrier, ///< Is a write barrier
162 IsReadBarrier, ///< Is a read barrier
163 IsERET, /// <- Causes the IFU to stall (MIPS ISA)
165 IsNonSpeculative, ///< Should not be executed speculatively
166 IsQuiesce, ///< Is a quiesce instruction
168 IsIprAccess, ///< Accesses IPRs
169 IsUnverifiable, ///< Can't be verified by a checker
171 IsSyscall, ///< Causes a system call to be emulated in syscall
174 //Flags for microcode
175 IsMacroop, ///< Is a macroop containing microops
176 IsMicroop, ///< Is a microop
177 IsDelayedCommit, ///< This microop doesn't commit right away
178 IsLastMicroop, ///< This microop ends a microop sequence
179 IsFirstMicroop, ///< This microop begins a microop sequence
180 //This flag doesn't do anything yet
181 IsMicroBranch, ///< This microop branches within the microcode for a macroop
187 /// Flag values for this instruction.
188 std::bitset<NumFlags> flags;
193 /// See numSrcRegs().
196 /// See numDestRegs().
199 /// The following are used to track physical register usage
200 /// for machines with separate int & FP reg files.
202 int8_t _numFPDestRegs;
203 int8_t _numIntDestRegs;
207 /// It's important to initialize everything here to a sane
208 /// default, since the decoder generally only overrides
209 /// the fields that are meaningful for the particular
211 StaticInstBase(OpClass __opClass)
212 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
213 _numFPDestRegs(0), _numIntDestRegs(0)
219 /// @name Register information.
220 /// The sum of numFPDestRegs() and numIntDestRegs() equals
221 /// numDestRegs(). The former two functions are used to track
222 /// physical register usage for machines with separate int & FP
225 /// Number of source registers.
226 int8_t numSrcRegs() const { return _numSrcRegs; }
227 /// Number of destination registers.
228 int8_t numDestRegs() const { return _numDestRegs; }
229 /// Number of floating-point destination regs.
230 int8_t numFPDestRegs() const { return _numFPDestRegs; }
231 /// Number of integer destination regs.
232 int8_t numIntDestRegs() const { return _numIntDestRegs; }
235 /// @name Flag accessors.
236 /// These functions are used to access the values of the various
237 /// instruction property flags. See StaticInstBase::Flags for descriptions
238 /// of the individual flags.
241 bool isNop() const { return flags[IsNop]; }
243 bool isMemRef() const { return flags[IsMemRef]; }
244 bool isLoad() const { return flags[IsLoad]; }
245 bool isStore() const { return flags[IsStore]; }
246 bool isStoreConditional() const { return flags[IsStoreConditional]; }
247 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
248 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
249 bool isCopy() const { return flags[IsCopy];}
251 bool isInteger() const { return flags[IsInteger]; }
252 bool isFloating() const { return flags[IsFloating]; }
254 bool isControl() const { return flags[IsControl]; }
255 bool isCall() const { return flags[IsCall]; }
256 bool isReturn() const { return flags[IsReturn]; }
257 bool isDirectCtrl() const { return flags[IsDirectControl]; }
258 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
259 bool isCondCtrl() const { return flags[IsCondControl]; }
260 bool isUncondCtrl() const { return flags[IsUncondControl]; }
261 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
263 bool isThreadSync() const { return flags[IsThreadSync]; }
264 bool isSerializing() const { return flags[IsSerializing] ||
265 flags[IsSerializeBefore] ||
266 flags[IsSerializeAfter]; }
267 bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
268 bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
269 bool isMemBarrier() const { return flags[IsMemBarrier]; }
270 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
271 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
272 bool isQuiesce() const { return flags[IsQuiesce]; }
273 bool isIprAccess() const { return flags[IsIprAccess]; }
274 bool isUnverifiable() const { return flags[IsUnverifiable]; }
275 bool isSyscall() const { return flags[IsSyscall]; }
276 bool isMacroop() const { return flags[IsMacroop]; }
277 bool isMicroop() const { return flags[IsMicroop]; }
278 bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
279 bool isLastMicroop() const { return flags[IsLastMicroop]; }
280 bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
281 //This flag doesn't do anything yet
282 bool isMicroBranch() const { return flags[IsMicroBranch]; }
285 void setLastMicroop() { flags[IsLastMicroop] = true; }
286 /// Operation class. Used to select appropriate function unit in issue.
287 OpClass opClass() const { return _opClass; }
291 // forward declaration
295 * Generic yet ISA-dependent static instruction class.
297 * This class builds on StaticInstBase, defining fields and interfaces
298 * that are generic across all ISAs but that differ in details
299 * according to the specific ISA being used.
301 class StaticInst : public StaticInstBase
305 /// Binary machine instruction type.
306 typedef TheISA::MachInst MachInst;
307 /// Binary extended machine instruction type.
308 typedef TheISA::ExtMachInst ExtMachInst;
309 /// Logical register index type.
310 typedef TheISA::RegIndex RegIndex;
313 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
314 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
318 /// Return logical index (architectural reg num) of i'th destination reg.
319 /// Only the entries from 0 through numDestRegs()-1 are valid.
320 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
322 /// Return logical index (architectural reg num) of i'th source reg.
323 /// Only the entries from 0 through numSrcRegs()-1 are valid.
324 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
326 /// Pointer to a statically allocated "null" instruction object.
327 /// Used to give eaCompInst() and memAccInst() something to return
328 /// when called on non-memory instructions.
329 static StaticInstPtr nullStaticInstPtr;
332 * Memory references only: returns "fake" instruction representing
333 * the effective address part of the memory operation. Used to
334 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
335 * just the EA computation.
338 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
341 * Memory references only: returns "fake" instruction representing
342 * the memory access part of the memory operation. Used to
343 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
344 * just the memory access (not the EA computation).
347 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
349 /// The binary machine instruction.
350 const ExtMachInst machInst;
354 /// See destRegIdx().
355 RegIndex _destRegIdx[MaxInstDestRegs];
357 RegIndex _srcRegIdx[MaxInstSrcRegs];
360 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
361 * methods. Also useful to readily identify instructions from
362 * within the debugger when #cachedDisassembly has not been
365 const char *mnemonic;
368 * String representation of disassembly (lazily evaluated via
371 mutable std::string *cachedDisassembly;
374 * Internal function to generate disassembly string.
377 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
380 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
381 : StaticInstBase(__opClass),
382 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
386 virtual ~StaticInst();
389 * The execute() signatures are auto-generated by scons based on the
390 * set of CPU models we are compiling in today.
392 #include "cpu/static_inst_exec_sigs.hh"
395 * Return the microop that goes with a particular micropc. This should
396 * only be defined/used in macroops which will contain microops
398 virtual StaticInstPtr fetchMicroop(MicroPC micropc);
401 * Return the target address for a PC-relative branch.
402 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
405 virtual Addr branchTarget(Addr branchPC) const;
408 * Return the target address for an indirect branch (jump). The
409 * register value is read from the supplied thread context, so
410 * the result is valid only if the thread context is about to
411 * execute the branch in question. Invalid if not an indirect
412 * branch (i.e. isIndirectCtrl() should be true).
414 virtual Addr branchTarget(ThreadContext *tc) const;
417 * Return true if the instruction is a control transfer, and if so,
418 * return the target address as well.
420 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
423 * Return string representation of disassembled instruction.
424 * The default version of this function will call the internal
425 * virtual generateDisassembly() function to get the string,
426 * then cache it in #cachedDisassembly. If the disassembly
427 * should not be cached, this function should be overridden directly.
429 virtual const std::string &disassemble(Addr pc,
430 const SymbolTable *symtab = 0) const;
432 /// Decoded instruction cache type.
433 /// For now we're using a generic hash_map; this seems to work
435 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
437 /// A cache of decoded instruction objects.
438 static DecodeCache decodeCache;
441 * Dump some basic stats on the decode cache hash map.
442 * Only gets called if DECODE_CACHE_HASH_STATS is defined.
444 static void dumpDecodeCacheStats();
446 /// Decode a machine instruction.
447 /// @param mach_inst The binary instruction to decode.
448 /// @retval A pointer to the corresponding StaticInst object.
449 //This is defined as inlined below.
450 static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
452 /// Return name of machine instruction
453 std::string getName() { return mnemonic; }
455 /// Decoded instruction cache type, for address decoding.
456 /// A generic hash_map is used.
457 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache;
459 /// A cache of decoded instruction objects from addresses.
460 static AddrDecodeCache addrDecodeCache;
465 AddrDecodePage *decodePage;
467 cacheElement() : decodePage(NULL) { }
470 /// An array of recently decoded instructions.
471 // might not use an array if there is only two elements
472 static struct cacheElement recentDecodes[2];
474 /// Updates the recently decoded instructions entries
475 /// @param page_addr The page address recently used.
476 /// @param decodePage Pointer to decoding page containing the decoded
479 updateCache(Addr page_addr, AddrDecodePage *decodePage)
481 recentDecodes[1].page_addr = recentDecodes[0].page_addr;
482 recentDecodes[1].decodePage = recentDecodes[0].decodePage;
483 recentDecodes[0].page_addr = page_addr;
484 recentDecodes[0].decodePage = decodePage;
487 /// Searches the decoded instruction cache for instruction decoding.
488 /// If it is not found, then we decode the instruction.
489 /// Otherwise, we get the instruction from the cache and move it into
490 /// the address-to-instruction decoding page.
491 /// @param mach_inst The binary instruction to decode.
492 /// @param addr The address that contained the binary instruction.
493 /// @param decodePage Pointer to decoding page containing the instruction.
494 /// @retval A pointer to the corresponding StaticInst object.
495 //This is defined as inlined below.
496 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr,
497 AddrDecodePage *decodePage);
500 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
502 /// Reference-counted pointer to a StaticInst object.
503 /// This type should be used instead of "StaticInst *" so that
504 /// StaticInst objects can be properly reference-counted.
505 class StaticInstPtr : public RefCountingPtr<StaticInst>
510 : RefCountingPtr<StaticInst>()
514 /// Conversion from "StaticInst *".
515 StaticInstPtr(StaticInst *p)
516 : RefCountingPtr<StaticInst>(p)
520 /// Copy constructor.
521 StaticInstPtr(const StaticInstPtr &r)
522 : RefCountingPtr<StaticInst>(r)
526 /// Construct directly from machine instruction.
527 /// Calls StaticInst::decode().
528 explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr)
529 : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr))
533 /// Convert to pointer to StaticInstBase class.
534 operator const StaticInstBasePtr()
540 /// A page of a list of decoded instructions from an address.
543 typedef TheISA::ExtMachInst ExtMachInst;
545 StaticInstPtr instructions[TheISA::PageBytes];
546 bool valid[TheISA::PageBytes];
553 lowerMask = TheISA::PageBytes - 1;
554 memset(valid, 0, TheISA::PageBytes);
557 /// Checks if the instruction is already decoded and the machine
558 /// instruction in the cache matches the current machine instruction
559 /// related to the address
560 /// @param mach_inst The binary instruction to check
561 /// @param addr The address containing the instruction
563 decoded(ExtMachInst mach_inst, Addr addr)
565 return (valid[addr & lowerMask] &&
566 (instructions[addr & lowerMask]->machInst == mach_inst));
569 /// Returns the instruction object. decoded should be called first
570 /// to check if the instruction is valid.
571 /// @param addr The address of the instruction.
572 /// @retval A pointer to the corresponding StaticInst object.
576 return instructions[addr & lowerMask];
579 /// Inserts a pointer to a StaticInst object into the list of decoded
580 /// instructions on the page.
581 /// @param addr The address of the instruction.
582 /// @param si A pointer to the corresponding StaticInst object.
584 insert(Addr addr, StaticInstPtr &si)
586 instructions[addr & lowerMask] = si;
587 valid[addr & lowerMask] = true;
593 StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
595 #ifdef DECODE_CACHE_HASH_STATS
596 // Simple stats on decode hash_map. Turns out the default
597 // hash function is as good as anything I could come up with.
598 const int dump_every_n = 10000000;
599 static int decodes_til_dump = dump_every_n;
601 if (--decodes_til_dump == 0) {
602 dumpDecodeCacheStats();
603 decodes_til_dump = dump_every_n;
607 Addr page_addr = addr & ~(TheISA::PageBytes - 1);
609 // checks recently decoded addresses
610 if (recentDecodes[0].decodePage &&
611 page_addr == recentDecodes[0].page_addr) {
612 if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
613 return recentDecodes[0].decodePage->getInst(addr);
615 return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
618 if (recentDecodes[1].decodePage &&
619 page_addr == recentDecodes[1].page_addr) {
620 if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
621 return recentDecodes[1].decodePage->getInst(addr);
623 return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
626 // searches the page containing the address to decode
627 AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr);
628 if (iter != addrDecodeCache.end()) {
629 updateCache(page_addr, iter->second);
630 if (iter->second->decoded(mach_inst, addr))
631 return iter->second->getInst(addr);
633 return searchCache(mach_inst, addr, iter->second);
636 // creates a new object for a page of decoded instructions
637 AddrDecodePage *decodePage = new AddrDecodePage;
638 addrDecodeCache[page_addr] = decodePage;
639 updateCache(page_addr, decodePage);
640 return searchCache(mach_inst, addr, decodePage);
644 StaticInst::searchCache(ExtMachInst mach_inst, Addr addr,
645 AddrDecodePage *decodePage)
647 DecodeCache::iterator iter = decodeCache.find(mach_inst);
648 if (iter != decodeCache.end()) {
649 decodePage->insert(addr, iter->second);
653 StaticInstPtr si = TheISA::decodeInst(mach_inst);
654 decodePage->insert(addr, si);
655 decodeCache[mach_inst] = si;
659 #endif // __CPU_STATIC_INST_HH__