src/cpu/static_inst.hh

   1 /*
   2  * Copyright (c) 2017 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Steve Reinhardt
  42  */
  43
  44 #ifndef __CPU_STATIC_INST_HH__
  45 #define __CPU_STATIC_INST_HH__
  46
  47 #include <bitset>
  48 #include <memory>
  49 #include <string>
  50
  51 #include "arch/registers.hh"
  52 #include "arch/types.hh"
  53 #include "base/logging.hh"
  54 #include "base/refcnt.hh"
  55 #include "base/types.hh"
  56 #include "config/the_isa.hh"
  57 #include "cpu/op_class.hh"
  58 #include "cpu/reg_class.hh"
  59 #include "cpu/static_inst_fwd.hh"
  60 #include "cpu/thread_context.hh"
  61 #include "enums/StaticInstFlags.hh"
  62 #include "sim/byteswap.hh"
  63
  64 // forward declarations
  65 class Packet;
  66
  67 class ExecContext;
  68
  69 class SymbolTable;
  70
  71 namespace Trace {
  72     class InstRecord;
  73 }
  74
  75 /**
  76  * Base, ISA-independent static instruction class.
  77  *
  78  * The main component of this class is the vector of flags and the
  79  * associated methods for reading them.  Any object that can rely
  80  * solely on these flags can process instructions without being
  81  * recompiled for multiple ISAs.
  82  */
  83 class StaticInst : public RefCounted, public StaticInstFlags
  84 {
  85   public:
  86     /// Binary extended machine instruction type.
  87     typedef TheISA::ExtMachInst ExtMachInst;
  88
  89     enum {
  90         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
  91         MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
  92     };
  93
  94   protected:
  95
  96     /// Flag values for this instruction.
  97     std::bitset<Num_Flags> flags;
  98
  99     /// See opClass().
 100     OpClass _opClass;
 101
 102     /// See numSrcRegs().
 103     int8_t _numSrcRegs;
 104
 105     /// See numDestRegs().
 106     int8_t _numDestRegs;
 107
 108     /// The following are used to track physical register usage
 109     /// for machines with separate int & FP reg files.
 110     //@{
 111     int8_t _numFPDestRegs;
 112     int8_t _numIntDestRegs;
 113     int8_t _numCCDestRegs;
 114     //@}
 115
 116     /** To use in architectures with vector register file. */
 117     /** @{ */
 118     int8_t _numVecDestRegs;
 119     int8_t _numVecElemDestRegs;
 120     int8_t _numVecPredDestRegs;
 121     /** @} */
 122
 123   public:
 124
 125     /// @name Register information.
 126     /// The sum of numFPDestRegs(), numIntDestRegs(), numVecDestRegs(),
 127     /// numVecElemDestRegs() and numVecPredDestRegs() equals numDestRegs().
 128     /// The former two functions are used to track physical register usage for
 129     /// machines with separate int & FP reg files, the next three are for
 130     /// machines with vector and predicate register files.
 131     //@{
 132     /// Number of source registers.
 133     int8_t numSrcRegs()  const { return _numSrcRegs; }
 134     /// Number of destination registers.
 135     int8_t numDestRegs() const { return _numDestRegs; }
 136     /// Number of floating-point destination regs.
 137     int8_t numFPDestRegs()  const { return _numFPDestRegs; }
 138     /// Number of integer destination regs.
 139     int8_t numIntDestRegs() const { return _numIntDestRegs; }
 140     /// Number of vector destination regs.
 141     int8_t numVecDestRegs() const { return _numVecDestRegs; }
 142     /// Number of vector element destination regs.
 143     int8_t numVecElemDestRegs() const { return _numVecElemDestRegs; }
 144     /// Number of predicate destination regs.
 145     int8_t numVecPredDestRegs() const { return _numVecPredDestRegs; }
 146     /// Number of coprocesor destination regs.
 147     int8_t numCCDestRegs() const { return _numCCDestRegs; }
 148     //@}
 149
 150     /// @name Flag accessors.
 151     /// These functions are used to access the values of the various
 152     /// instruction property flags.  See StaticInst::Flags for descriptions
 153     /// of the individual flags.
 154     //@{
 155
 156     bool isNop()          const { return flags[IsNop]; }
 157
 158     bool isMemRef()       const { return flags[IsMemRef]; }
 159     bool isLoad()         const { return flags[IsLoad]; }
 160     bool isStore()        const { return flags[IsStore]; }
 161     bool isAtomic()       const { return flags[IsAtomic]; }
 162     bool isStoreConditional()     const { return flags[IsStoreConditional]; }
 163     bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
 164     bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
 165     bool isPrefetch()     const { return isInstPrefetch() ||
 166                                          isDataPrefetch(); }
 167
 168     bool isInteger()      const { return flags[IsInteger]; }
 169     bool isFloating()     const { return flags[IsFloating]; }
 170     bool isVector()       const { return flags[IsVector]; }
 171     bool isCC()           const { return flags[IsCC]; }
 172
 173     bool isControl()      const { return flags[IsControl]; }
 174     bool isCall()         const { return flags[IsCall]; }
 175     bool isReturn()       const { return flags[IsReturn]; }
 176     bool isDirectCtrl()   const { return flags[IsDirectControl]; }
 177     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
 178     bool isCondCtrl()     const { return flags[IsCondControl]; }
 179     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 180     bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
 181
 182     bool isThreadSync()   const { return flags[IsThreadSync]; }
 183     bool isSerializing()  const { return flags[IsSerializing] ||
 184                                       flags[IsSerializeBefore] ||
 185                                       flags[IsSerializeAfter]; }
 186     bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
 187     bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
 188     bool isSquashAfter() const { return flags[IsSquashAfter]; }
 189     bool isMemBarrier()   const { return flags[IsMemBarrier]; }
 190     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
 191     bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
 192     bool isQuiesce() const { return flags[IsQuiesce]; }
 193     bool isIprAccess() const { return flags[IsIprAccess]; }
 194     bool isUnverifiable() const { return flags[IsUnverifiable]; }
 195     bool isSyscall() const { return flags[IsSyscall]; }
 196     bool isMacroop() const { return flags[IsMacroop]; }
 197     bool isMicroop() const { return flags[IsMicroop]; }
 198     bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
 199     bool isLastMicroop() const { return flags[IsLastMicroop]; }
 200     bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
 201     //This flag doesn't do anything yet
 202     bool isMicroBranch() const { return flags[IsMicroBranch]; }
 203     //@}
 204
 205     void setFirstMicroop() { flags[IsFirstMicroop] = true; }
 206     void setLastMicroop() { flags[IsLastMicroop] = true; }
 207     void setDelayedCommit() { flags[IsDelayedCommit] = true; }
 208     void setFlag(Flags f) { flags[f] = true; }
 209
 210     /// Operation class.  Used to select appropriate function unit in issue.
 211     OpClass opClass()     const { return _opClass; }
 212
 213
 214     /// Return logical index (architectural reg num) of i'th destination reg.
 215     /// Only the entries from 0 through numDestRegs()-1 are valid.
 216     const RegId& destRegIdx(int i) const { return _destRegIdx[i]; }
 217
 218     /// Return logical index (architectural reg num) of i'th source reg.
 219     /// Only the entries from 0 through numSrcRegs()-1 are valid.
 220     const RegId& srcRegIdx(int i)  const { return _srcRegIdx[i]; }
 221
 222     /// Pointer to a statically allocated "null" instruction object.
 223     static StaticInstPtr nullStaticInstPtr;
 224
 225     /// Pointer to a statically allocated generic "nop" instruction object.
 226     static StaticInstPtr nopStaticInstPtr;
 227
 228     /// The binary machine instruction.
 229     const ExtMachInst machInst;
 230
 231   protected:
 232
 233     /// See destRegIdx().
 234     RegId _destRegIdx[MaxInstDestRegs];
 235     /// See srcRegIdx().
 236     RegId _srcRegIdx[MaxInstSrcRegs];
 237
 238     /**
 239      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
 240      * methods.  Also useful to readily identify instructions from
 241      * within the debugger when #cachedDisassembly has not been
 242      * initialized.
 243      */
 244     const char *mnemonic;
 245
 246     /**
 247      * String representation of disassembly (lazily evaluated via
 248      * disassemble()).
 249      */
 250     mutable std::string *cachedDisassembly;
 251
 252     /**
 253      * Internal function to generate disassembly string.
 254      */
 255     virtual std::string
 256     generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 257
 258     /// Constructor.
 259     /// It's important to initialize everything here to a sane
 260     /// default, since the decoder generally only overrides
 261     /// the fields that are meaningful for the particular
 262     /// instruction.
 263     StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
 264         : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
 265           _numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0),
 266           _numVecDestRegs(0), _numVecElemDestRegs(0), _numVecPredDestRegs(0),
 267           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
 268     { }
 269
 270   public:
 271     virtual ~StaticInst();
 272
 273     virtual Fault execute(ExecContext *xc,
 274                           Trace::InstRecord *traceData) const = 0;
 275
 276     virtual Fault initiateAcc(ExecContext *xc,
 277                               Trace::InstRecord *traceData) const
 278     {
 279         panic("initiateAcc not defined!");
 280     }
 281
 282     virtual Fault completeAcc(Packet *pkt, ExecContext *xc,
 283                               Trace::InstRecord *traceData) const
 284     {
 285         panic("completeAcc not defined!");
 286     }
 287
 288     virtual void advancePC(TheISA::PCState &pcState) const = 0;
 289
 290     /**
 291      * Return the microop that goes with a particular micropc. This should
 292      * only be defined/used in macroops which will contain microops
 293      */
 294     virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
 295
 296     /**
 297      * Return the target address for a PC-relative branch.
 298      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
 299      * should be true).
 300      */
 301     virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
 302
 303     /**
 304      * Return the target address for an indirect branch (jump).  The
 305      * register value is read from the supplied thread context, so
 306      * the result is valid only if the thread context is about to
 307      * execute the branch in question.  Invalid if not an indirect
 308      * branch (i.e. isIndirectCtrl() should be true).
 309      */
 310     virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
 311
 312     /**
 313      * Return true if the instruction is a control transfer, and if so,
 314      * return the target address as well.
 315      */
 316     bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
 317                          TheISA::PCState &tgt) const;
 318
 319     /**
 320      * Return string representation of disassembled instruction.
 321      * The default version of this function will call the internal
 322      * virtual generateDisassembly() function to get the string,
 323      * then cache it in #cachedDisassembly.  If the disassembly
 324      * should not be cached, this function should be overridden directly.
 325      */
 326     virtual const std::string &disassemble(Addr pc,
 327         const SymbolTable *symtab = 0) const;
 328
 329     /**
 330      * Print a separator separated list of this instruction's set flag
 331      * names on the given stream.
 332      */
 333     void printFlags(std::ostream &outs, const std::string &separator) const;
 334
 335     /// Return name of machine instruction
 336     std::string getName() { return mnemonic; }
 337
 338   protected:
 339     template<typename T>
 340     size_t
 341     simpleAsBytes(void *buf, size_t max_size, const T &t)
 342     {
 343         size_t size = sizeof(T);
 344         if (size <= max_size)
 345             *reinterpret_cast<T *>(buf) = htole<T>(t);
 346         return size;
 347     }
 348
 349   public:
 350     /**
 351      * Instruction classes can override this function to return a
 352      * a representation of themselves as a blob of bytes, generally assumed to
 353      * be that instructions ExtMachInst.
 354      *
 355      * buf is a buffer to hold the bytes.
 356      * max_size is the size allocated for that buffer by the caller.
 357      * The return value is how much data was actually put into the buffer,
 358      * zero if no data was put in the buffer, or the necessary size of the
 359      * buffer if there wasn't enough space.
 360      */
 361     virtual size_t asBytes(void *buf, size_t max_size) { return 0; }
 362 };
 363
 364 #endif // __CPU_STATIC_INST_HH__