src/cpu/static_inst.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #ifndef __CPU_STATIC_INST_HH__
  32 #define __CPU_STATIC_INST_HH__
  33
  34 #include <bitset>
  35 #include <string>
  36
  37 #include "arch/isa_traits.hh"
  38 #include "arch/utility.hh"
  39 #include "sim/faults.hh"
  40 #include "base/bitfield.hh"
  41 #include "base/hashmap.hh"
  42 #include "base/misc.hh"
  43 #include "base/refcnt.hh"
  44 #include "cpu/op_class.hh"
  45 #include "cpu/o3/dyn_inst.hh"
  46 #include "sim/faults.hh"
  47 #include "sim/host.hh"
  48
  49 // forward declarations
  50 struct AlphaSimpleImpl;
  51 struct OzoneImpl;
  52 struct SimpleImpl;
  53 class ThreadContext;
  54 class DynInst;
  55 class Packet;
  56
  57 template <class Impl>
  58 class OzoneDynInst;
  59
  60 class CheckerCPU;
  61 class FastCPU;
  62 class AtomicSimpleCPU;
  63 class TimingSimpleCPU;
  64 class InorderCPU;
  65 class SymbolTable;
  66 class AddrDecodePage;
  67
  68 namespace Trace {
  69     class InstRecord;
  70 }
  71
  72 typedef uint32_t MicroPC;
  73
  74 /**
  75  * Base, ISA-independent static instruction class.
  76  *
  77  * The main component of this class is the vector of flags and the
  78  * associated methods for reading them.  Any object that can rely
  79  * solely on these flags can process instructions without being
  80  * recompiled for multiple ISAs.
  81  */
  82 class StaticInstBase : public RefCounted
  83 {
  84   protected:
  85
  86     /// Set of boolean static instruction properties.
  87     ///
  88     /// Notes:
  89     /// - The IsInteger and IsFloating flags are based on the class of
  90     /// registers accessed by the instruction.  Although most
  91     /// instructions will have exactly one of these two flags set, it
  92     /// is possible for an instruction to have neither (e.g., direct
  93     /// unconditional branches, memory barriers) or both (e.g., an
  94     /// FP/int conversion).
  95     /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
  96     /// will be set.
  97     /// - If IsControl is set, then exactly one of IsDirectControl or
  98     /// IsIndirect Control will be set, and exactly one of
  99     /// IsCondControl or IsUncondControl will be set.
 100     /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
 101     /// implemented as flags since in the current model there's no
 102     /// other way for instructions to inject behavior into the
 103     /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
 104     /// model we should be able to get rid of these flags and
 105     /// implement this behavior via the execute() methods.
 106     ///
 107     enum Flags {
 108         IsNop,          ///< Is a no-op (no effect at all).
 109
 110         IsInteger,      ///< References integer regs.
 111         IsFloating,     ///< References FP regs.
 112
 113         IsMemRef,       ///< References memory (load, store, or prefetch).
 114         IsLoad,         ///< Reads from memory (load or prefetch).
 115         IsStore,        ///< Writes to memory.
 116         IsStoreConditional,    ///< Store conditional instruction.
 117         IsInstPrefetch, ///< Instruction-cache prefetch.
 118         IsDataPrefetch, ///< Data-cache prefetch.
 119         IsCopy,         ///< Fast Cache block copy
 120
 121         IsControl,              ///< Control transfer instruction.
 122         IsDirectControl,        ///< PC relative control transfer.
 123         IsIndirectControl,      ///< Register indirect control transfer.
 124         IsCondControl,          ///< Conditional control transfer.
 125         IsUncondControl,        ///< Unconditional control transfer.
 126         IsCall,                 ///< Subroutine call.
 127         IsReturn,               ///< Subroutine return.
 128
 129         IsCondDelaySlot,///< Conditional Delay-Slot Instruction
 130
 131         IsThreadSync,   ///< Thread synchronization operation.
 132
 133         IsSerializing,  ///< Serializes pipeline: won't execute until all
 134                         /// older instructions have committed.
 135         IsSerializeBefore,
 136         IsSerializeAfter,
 137         IsMemBarrier,   ///< Is a memory barrier
 138         IsWriteBarrier, ///< Is a write barrier
 139
 140         IsNonSpeculative, ///< Should not be executed speculatively
 141         IsQuiesce,      ///< Is a quiesce instruction
 142
 143         IsIprAccess,    ///< Accesses IPRs
 144         IsUnverifiable, ///< Can't be verified by a checker
 145
 146         IsSyscall,      ///< Causes a system call to be emulated in syscall
 147                         /// emulation mode.
 148
 149         //Flags for microcode
 150         IsMacroop,      ///< Is a macroop containing microops
 151         IsMicroop,      ///< Is a microop
 152         IsDelayedCommit,        ///< This microop doesn't commit right away
 153         IsLastMicroop,  ///< This microop ends a microop sequence
 154         IsFirstMicroop, ///< This microop begins a microop sequence
 155         //This flag doesn't do anything yet
 156         IsMicroBranch,  ///< This microop branches within the microcode for a macroop
 157
 158         NumFlags
 159     };
 160
 161     /// Flag values for this instruction.
 162     std::bitset<NumFlags> flags;
 163
 164     /// See opClass().
 165     OpClass _opClass;
 166
 167     /// See numSrcRegs().
 168     int8_t _numSrcRegs;
 169
 170     /// See numDestRegs().
 171     int8_t _numDestRegs;
 172
 173     /// The following are used to track physical register usage
 174     /// for machines with separate int & FP reg files.
 175     //@{
 176     int8_t _numFPDestRegs;
 177     int8_t _numIntDestRegs;
 178     //@}
 179
 180     /// Constructor.
 181     /// It's important to initialize everything here to a sane
 182     /// default, since the decoder generally only overrides
 183     /// the fields that are meaningful for the particular
 184     /// instruction.
 185     StaticInstBase(OpClass __opClass)
 186         : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
 187           _numFPDestRegs(0), _numIntDestRegs(0)
 188     {
 189     }
 190
 191   public:
 192
 193     /// @name Register information.
 194     /// The sum of numFPDestRegs() and numIntDestRegs() equals
 195     /// numDestRegs().  The former two functions are used to track
 196     /// physical register usage for machines with separate int & FP
 197     /// reg files.
 198     //@{
 199     /// Number of source registers.
 200     int8_t numSrcRegs()  const { return _numSrcRegs; }
 201     /// Number of destination registers.
 202     int8_t numDestRegs() const { return _numDestRegs; }
 203     /// Number of floating-point destination regs.
 204     int8_t numFPDestRegs()  const { return _numFPDestRegs; }
 205     /// Number of integer destination regs.
 206     int8_t numIntDestRegs() const { return _numIntDestRegs; }
 207     //@}
 208
 209     /// @name Flag accessors.
 210     /// These functions are used to access the values of the various
 211     /// instruction property flags.  See StaticInstBase::Flags for descriptions
 212     /// of the individual flags.
 213     //@{
 214
 215     bool isNop()          const { return flags[IsNop]; }
 216
 217     bool isMemRef()       const { return flags[IsMemRef]; }
 218     bool isLoad()         const { return flags[IsLoad]; }
 219     bool isStore()        const { return flags[IsStore]; }
 220     bool isStoreConditional()     const { return flags[IsStoreConditional]; }
 221     bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
 222     bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
 223     bool isCopy()         const { return flags[IsCopy];}
 224
 225     bool isInteger()      const { return flags[IsInteger]; }
 226     bool isFloating()     const { return flags[IsFloating]; }
 227
 228     bool isControl()      const { return flags[IsControl]; }
 229     bool isCall()         const { return flags[IsCall]; }
 230     bool isReturn()       const { return flags[IsReturn]; }
 231     bool isDirectCtrl()   const { return flags[IsDirectControl]; }
 232     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
 233     bool isCondCtrl()     const { return flags[IsCondControl]; }
 234     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 235     bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
 236
 237     bool isThreadSync()   const { return flags[IsThreadSync]; }
 238     bool isSerializing()  const { return flags[IsSerializing] ||
 239                                       flags[IsSerializeBefore] ||
 240                                       flags[IsSerializeAfter]; }
 241     bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
 242     bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
 243     bool isMemBarrier()   const { return flags[IsMemBarrier]; }
 244     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
 245     bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
 246     bool isQuiesce() const { return flags[IsQuiesce]; }
 247     bool isIprAccess() const { return flags[IsIprAccess]; }
 248     bool isUnverifiable() const { return flags[IsUnverifiable]; }
 249     bool isSyscall() const { return flags[IsSyscall]; }
 250     bool isMacroop() const { return flags[IsMacroop]; }
 251     bool isMicroop() const { return flags[IsMicroop]; }
 252     bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
 253     bool isLastMicroop() const { return flags[IsLastMicroop]; }
 254     bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
 255     //This flag doesn't do anything yet
 256     bool isMicroBranch() const { return flags[IsMicroBranch]; }
 257     //@}
 258
 259     /// Operation class.  Used to select appropriate function unit in issue.
 260     OpClass opClass()     const { return _opClass; }
 261 };
 262
 263
 264 // forward declaration
 265 class StaticInstPtr;
 266
 267 /**
 268  * Generic yet ISA-dependent static instruction class.
 269  *
 270  * This class builds on StaticInstBase, defining fields and interfaces
 271  * that are generic across all ISAs but that differ in details
 272  * according to the specific ISA being used.
 273  */
 274 class StaticInst : public StaticInstBase
 275 {
 276   public:
 277
 278     /// Binary machine instruction type.
 279     typedef TheISA::MachInst MachInst;
 280     /// Binary extended machine instruction type.
 281     typedef TheISA::ExtMachInst ExtMachInst;
 282     /// Logical register index type.
 283     typedef TheISA::RegIndex RegIndex;
 284
 285     enum {
 286         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
 287         MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
 288     };
 289
 290
 291     /// Return logical index (architectural reg num) of i'th destination reg.
 292     /// Only the entries from 0 through numDestRegs()-1 are valid.
 293     RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
 294
 295     /// Return logical index (architectural reg num) of i'th source reg.
 296     /// Only the entries from 0 through numSrcRegs()-1 are valid.
 297     RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
 298
 299     /// Pointer to a statically allocated "null" instruction object.
 300     /// Used to give eaCompInst() and memAccInst() something to return
 301     /// when called on non-memory instructions.
 302     static StaticInstPtr nullStaticInstPtr;
 303
 304     /**
 305      * Memory references only: returns "fake" instruction representing
 306      * the effective address part of the memory operation.  Used to
 307      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 308      * just the EA computation.
 309      */
 310     virtual const
 311     StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
 312
 313     /**
 314      * Memory references only: returns "fake" instruction representing
 315      * the memory access part of the memory operation.  Used to
 316      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 317      * just the memory access (not the EA computation).
 318      */
 319     virtual const
 320     StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
 321
 322     /// The binary machine instruction.
 323     const ExtMachInst machInst;
 324
 325   protected:
 326
 327     /// See destRegIdx().
 328     RegIndex _destRegIdx[MaxInstDestRegs];
 329     /// See srcRegIdx().
 330     RegIndex _srcRegIdx[MaxInstSrcRegs];
 331
 332     /**
 333      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
 334      * methods.  Also useful to readily identify instructions from
 335      * within the debugger when #cachedDisassembly has not been
 336      * initialized.
 337      */
 338     const char *mnemonic;
 339
 340     /**
 341      * String representation of disassembly (lazily evaluated via
 342      * disassemble()).
 343      */
 344     mutable std::string *cachedDisassembly;
 345
 346     /**
 347      * Internal function to generate disassembly string.
 348      */
 349     virtual std::string
 350     generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 351
 352     /// Constructor.
 353     StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
 354         : StaticInstBase(__opClass),
 355           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
 356     { }
 357
 358   public:
 359
 360     virtual ~StaticInst()
 361     {
 362         if (cachedDisassembly)
 363             delete cachedDisassembly;
 364     }
 365
 366 /**
 367  * The execute() signatures are auto-generated by scons based on the
 368  * set of CPU models we are compiling in today.
 369  */
 370 #include "cpu/static_inst_exec_sigs.hh"
 371
 372     /**
 373      * Return the microop that goes with a particular micropc. This should
 374      * only be defined/used in macroops which will contain microops
 375      */
 376     virtual StaticInstPtr fetchMicroop(MicroPC micropc);
 377
 378     /**
 379      * Return the target address for a PC-relative branch.
 380      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
 381      * should be true).
 382      */
 383     virtual Addr branchTarget(Addr branchPC) const
 384     {
 385         panic("StaticInst::branchTarget() called on instruction "
 386               "that is not a PC-relative branch.");
 387         M5_DUMMY_RETURN
 388     }
 389
 390     /**
 391      * Return the target address for an indirect branch (jump).  The
 392      * register value is read from the supplied thread context, so
 393      * the result is valid only if the thread context is about to
 394      * execute the branch in question.  Invalid if not an indirect
 395      * branch (i.e. isIndirectCtrl() should be true).
 396      */
 397     virtual Addr branchTarget(ThreadContext *tc) const
 398     {
 399         panic("StaticInst::branchTarget() called on instruction "
 400               "that is not an indirect branch.");
 401     }
 402         M5_DUMMY_RETURN
 403
 404     /**
 405      * Return true if the instruction is a control transfer, and if so,
 406      * return the target address as well.
 407      */
 408     bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
 409
 410     /**
 411      * Return string representation of disassembled instruction.
 412      * The default version of this function will call the internal
 413      * virtual generateDisassembly() function to get the string,
 414      * then cache it in #cachedDisassembly.  If the disassembly
 415      * should not be cached, this function should be overridden directly.
 416      */
 417     virtual const std::string &disassemble(Addr pc,
 418                                            const SymbolTable *symtab = 0) const
 419     {
 420         if (!cachedDisassembly)
 421             cachedDisassembly =
 422                 new std::string(generateDisassembly(pc, symtab));
 423
 424         return *cachedDisassembly;
 425     }
 426
 427     /// Decoded instruction cache type.
 428     /// For now we're using a generic hash_map; this seems to work
 429     /// pretty well.
 430     typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
 431
 432     /// A cache of decoded instruction objects.
 433     static DecodeCache decodeCache;
 434
 435     /**
 436      * Dump some basic stats on the decode cache hash map.
 437      * Only gets called if DECODE_CACHE_HASH_STATS is defined.
 438      */
 439     static void dumpDecodeCacheStats();
 440
 441     /// Decode a machine instruction.
 442     /// @param mach_inst The binary instruction to decode.
 443     /// @retval A pointer to the corresponding StaticInst object.
 444     //This is defined as inlined below.
 445     static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
 446
 447     /// Return name of machine instruction
 448     std::string getName() { return mnemonic; }
 449
 450     /// Decoded instruction cache type, for address decoding.
 451     /// A generic hash_map is used.
 452     typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache;
 453
 454     /// A cache of decoded instruction objects from addresses.
 455     static AddrDecodeCache addrDecodeCache;
 456
 457     struct cacheElement {
 458         Addr page_addr;
 459         AddrDecodePage *decodePage;
 460
 461         cacheElement()
 462           :decodePage(NULL) { }
 463     } ;
 464
 465     /// An array of recently decoded instructions.
 466     // might not use an array if there is only two elements
 467     static struct cacheElement recentDecodes[2];
 468
 469     /// Updates the recently decoded instructions entries
 470     /// @param page_addr The page address recently used.
 471     /// @param decodePage Pointer to decoding page containing the decoded
 472     ///                   instruction.
 473     static inline void
 474     updateCache(Addr page_addr, AddrDecodePage *decodePage)
 475     {
 476         recentDecodes[1].page_addr = recentDecodes[0].page_addr;
 477         recentDecodes[1].decodePage = recentDecodes[0].decodePage;
 478         recentDecodes[0].page_addr = page_addr;
 479         recentDecodes[0].decodePage = decodePage;
 480     }
 481
 482     /// Searches the decoded instruction cache for instruction decoding.
 483     /// If it is not found, then we decode the instruction.
 484     /// Otherwise, we get the instruction from the cache and move it into
 485     /// the address-to-instruction decoding page.
 486     /// @param mach_inst The binary instruction to decode.
 487     /// @param addr The address that contained the binary instruction.
 488     /// @param decodePage Pointer to decoding page containing the instruction.
 489     /// @retval A pointer to the corresponding StaticInst object.
 490     //This is defined as inlined below.
 491     static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr,
 492                                      AddrDecodePage * decodePage);
 493 };
 494
 495 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
 496
 497 /// Reference-counted pointer to a StaticInst object.
 498 /// This type should be used instead of "StaticInst *" so that
 499 /// StaticInst objects can be properly reference-counted.
 500 class StaticInstPtr : public RefCountingPtr<StaticInst>
 501 {
 502   public:
 503     /// Constructor.
 504     StaticInstPtr()
 505         : RefCountingPtr<StaticInst>()
 506     {
 507     }
 508
 509     /// Conversion from "StaticInst *".
 510     StaticInstPtr(StaticInst *p)
 511         : RefCountingPtr<StaticInst>(p)
 512     {
 513     }
 514
 515     /// Copy constructor.
 516     StaticInstPtr(const StaticInstPtr &r)
 517         : RefCountingPtr<StaticInst>(r)
 518     {
 519     }
 520
 521     /// Construct directly from machine instruction.
 522     /// Calls StaticInst::decode().
 523     explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr)
 524         : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr))
 525     {
 526     }
 527
 528     /// Convert to pointer to StaticInstBase class.
 529     operator const StaticInstBasePtr()
 530     {
 531         return this->get();
 532     }
 533 };
 534
 535 /// A page of a list of decoded instructions from an address.
 536 class AddrDecodePage
 537 {
 538   typedef TheISA::ExtMachInst ExtMachInst;
 539   protected:
 540     StaticInstPtr instructions[TheISA::PageBytes];
 541     bool valid[TheISA::PageBytes];
 542     Addr lowerMask;
 543
 544   public:
 545     /// Constructor
 546     AddrDecodePage() {
 547         lowerMask = TheISA::PageBytes - 1;
 548         memset(valid, 0, TheISA::PageBytes);
 549     }
 550
 551     /// Checks if the instruction is already decoded and the machine
 552     /// instruction in the cache matches the current machine instruction
 553     /// related to the address
 554     /// @param mach_inst The binary instruction to check
 555     /// @param addr The address containing the instruction
 556     inline bool decoded(ExtMachInst mach_inst, Addr addr)
 557     {
 558         return (valid[addr & lowerMask] &&
 559                 (instructions[addr & lowerMask]->machInst == mach_inst));
 560     }
 561
 562     /// Returns the instruction object. decoded should be called first
 563     /// to check if the instruction is valid.
 564     /// @param addr The address of the instruction.
 565     /// @retval A pointer to the corresponding StaticInst object.
 566     inline StaticInstPtr getInst(Addr addr)
 567     {   return instructions[addr & lowerMask]; }
 568
 569     /// Inserts a pointer to a StaticInst object into the list of decoded
 570     /// instructions on the page.
 571     /// @param addr The address of the instruction.
 572     /// @param si A pointer to the corresponding StaticInst object.
 573     inline void insert(Addr addr, StaticInstPtr &si)
 574     {
 575         instructions[addr & lowerMask] = si;
 576         valid[addr & lowerMask] = true;
 577     }
 578
 579 };
 580
 581
 582 inline StaticInstPtr
 583 StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
 584 {
 585 #ifdef DECODE_CACHE_HASH_STATS
 586     // Simple stats on decode hash_map.  Turns out the default
 587     // hash function is as good as anything I could come up with.
 588     const int dump_every_n = 10000000;
 589     static int decodes_til_dump = dump_every_n;
 590
 591     if (--decodes_til_dump == 0) {
 592         dumpDecodeCacheStats();
 593         decodes_til_dump = dump_every_n;
 594     }
 595 #endif
 596
 597     Addr page_addr = addr & ~(TheISA::PageBytes - 1);
 598
 599     // checks recently decoded addresses
 600     if (recentDecodes[0].decodePage &&
 601         page_addr == recentDecodes[0].page_addr) {
 602         if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
 603             return recentDecodes[0].decodePage->getInst(addr);
 604
 605         return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
 606     }
 607
 608     if (recentDecodes[1].decodePage &&
 609         page_addr == recentDecodes[1].page_addr) {
 610         if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
 611             return recentDecodes[1].decodePage->getInst(addr);
 612
 613         return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
 614     }
 615
 616     // searches the page containing the address to decode
 617     AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr);
 618     if (iter != addrDecodeCache.end()) {
 619         updateCache(page_addr, iter->second);
 620         if (iter->second->decoded(mach_inst, addr))
 621             return iter->second->getInst(addr);
 622
 623         return searchCache(mach_inst, addr, iter->second);
 624     }
 625
 626     // creates a new object for a page of decoded instructions
 627     AddrDecodePage * decodePage = new AddrDecodePage;
 628     addrDecodeCache[page_addr] = decodePage;
 629     updateCache(page_addr, decodePage);
 630     return searchCache(mach_inst, addr, decodePage);
 631 }
 632
 633 inline StaticInstPtr
 634 StaticInst::searchCache(ExtMachInst mach_inst, Addr addr,
 635                         AddrDecodePage * decodePage)
 636 {
 637     DecodeCache::iterator iter = decodeCache.find(mach_inst);
 638     if (iter != decodeCache.end()) {
 639         decodePage->insert(addr, iter->second);
 640         return iter->second;
 641     }
 642
 643     StaticInstPtr si = TheISA::decodeInst(mach_inst);
 644     decodePage->insert(addr, si);
 645     decodeCache[mach_inst] = si;
 646     return si;
 647 }
 648
 649 #endif // __CPU_STATIC_INST_HH__