src/cpu/static_inst.hh

   1 /*
   2  * Copyright (c) 2017 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
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  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __CPU_STATIC_INST_HH__
  43 #define __CPU_STATIC_INST_HH__
  44
  45 #include <bitset>
  46 #include <memory>
  47 #include <string>
  48
  49 #include "arch/registers.hh"
  50 #include "arch/types.hh"
  51 #include "base/logging.hh"
  52 #include "base/refcnt.hh"
  53 #include "base/types.hh"
  54 #include "config/the_isa.hh"
  55 #include "cpu/op_class.hh"
  56 #include "cpu/reg_class.hh"
  57 #include "cpu/static_inst_fwd.hh"
  58 #include "cpu/thread_context.hh"
  59 #include "enums/StaticInstFlags.hh"
  60 #include "sim/byteswap.hh"
  61
  62 // forward declarations
  63 class Packet;
  64
  65 class ExecContext;
  66
  67 class SymbolTable;
  68
  69 namespace Trace {
  70     class InstRecord;
  71 }
  72
  73 /**
  74  * Base, ISA-independent static instruction class.
  75  *
  76  * The main component of this class is the vector of flags and the
  77  * associated methods for reading them.  Any object that can rely
  78  * solely on these flags can process instructions without being
  79  * recompiled for multiple ISAs.
  80  */
  81 class StaticInst : public RefCounted, public StaticInstFlags
  82 {
  83   public:
  84     /// Binary extended machine instruction type.
  85     typedef TheISA::ExtMachInst ExtMachInst;
  86
  87     enum {
  88         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
  89         MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
  90     };
  91
  92   protected:
  93
  94     /// Flag values for this instruction.
  95     std::bitset<Num_Flags> flags;
  96
  97     /// See opClass().
  98     OpClass _opClass;
  99
 100     /// See numSrcRegs().
 101     int8_t _numSrcRegs;
 102
 103     /// See numDestRegs().
 104     int8_t _numDestRegs;
 105
 106     /// The following are used to track physical register usage
 107     /// for machines with separate int & FP reg files.
 108     //@{
 109     int8_t _numFPDestRegs;
 110     int8_t _numIntDestRegs;
 111     int8_t _numCCDestRegs;
 112     //@}
 113
 114     /** To use in architectures with vector register file. */
 115     /** @{ */
 116     int8_t _numVecDestRegs;
 117     int8_t _numVecElemDestRegs;
 118     int8_t _numVecPredDestRegs;
 119     /** @} */
 120
 121   public:
 122
 123     /// @name Register information.
 124     /// The sum of numFPDestRegs(), numIntDestRegs(), numVecDestRegs(),
 125     /// numVecElemDestRegs() and numVecPredDestRegs() equals numDestRegs().
 126     /// The former two functions are used to track physical register usage for
 127     /// machines with separate int & FP reg files, the next three are for
 128     /// machines with vector and predicate register files.
 129     //@{
 130     /// Number of source registers.
 131     int8_t numSrcRegs()  const { return _numSrcRegs; }
 132     /// Number of destination registers.
 133     int8_t numDestRegs() const { return _numDestRegs; }
 134     /// Number of floating-point destination regs.
 135     int8_t numFPDestRegs()  const { return _numFPDestRegs; }
 136     /// Number of integer destination regs.
 137     int8_t numIntDestRegs() const { return _numIntDestRegs; }
 138     /// Number of vector destination regs.
 139     int8_t numVecDestRegs() const { return _numVecDestRegs; }
 140     /// Number of vector element destination regs.
 141     int8_t numVecElemDestRegs() const { return _numVecElemDestRegs; }
 142     /// Number of predicate destination regs.
 143     int8_t numVecPredDestRegs() const { return _numVecPredDestRegs; }
 144     /// Number of coprocesor destination regs.
 145     int8_t numCCDestRegs() const { return _numCCDestRegs; }
 146     //@}
 147
 148     /// @name Flag accessors.
 149     /// These functions are used to access the values of the various
 150     /// instruction property flags.  See StaticInst::Flags for descriptions
 151     /// of the individual flags.
 152     //@{
 153
 154     bool isNop()          const { return flags[IsNop]; }
 155
 156     bool isMemRef()       const { return flags[IsMemRef]; }
 157     bool isLoad()         const { return flags[IsLoad]; }
 158     bool isStore()        const { return flags[IsStore]; }
 159     bool isAtomic()       const { return flags[IsAtomic]; }
 160     bool isStoreConditional()     const { return flags[IsStoreConditional]; }
 161     bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
 162     bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
 163     bool isPrefetch()     const { return isInstPrefetch() ||
 164                                          isDataPrefetch(); }
 165
 166     bool isInteger()      const { return flags[IsInteger]; }
 167     bool isFloating()     const { return flags[IsFloating]; }
 168     bool isVector()       const { return flags[IsVector]; }
 169     bool isCC()           const { return flags[IsCC]; }
 170
 171     bool isControl()      const { return flags[IsControl]; }
 172     bool isCall()         const { return flags[IsCall]; }
 173     bool isReturn()       const { return flags[IsReturn]; }
 174     bool isDirectCtrl()   const { return flags[IsDirectControl]; }
 175     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
 176     bool isCondCtrl()     const { return flags[IsCondControl]; }
 177     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 178     bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
 179
 180     bool isThreadSync()   const { return flags[IsThreadSync]; }
 181     bool isSerializing()  const { return flags[IsSerializing] ||
 182                                       flags[IsSerializeBefore] ||
 183                                       flags[IsSerializeAfter]; }
 184     bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
 185     bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
 186     bool isSquashAfter() const { return flags[IsSquashAfter]; }
 187     bool isMemBarrier()   const { return flags[IsMemBarrier]; }
 188     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
 189     bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
 190     bool isQuiesce() const { return flags[IsQuiesce]; }
 191     bool isIprAccess() const { return flags[IsIprAccess]; }
 192     bool isUnverifiable() const { return flags[IsUnverifiable]; }
 193     bool isSyscall() const { return flags[IsSyscall]; }
 194     bool isMacroop() const { return flags[IsMacroop]; }
 195     bool isMicroop() const { return flags[IsMicroop]; }
 196     bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
 197     bool isLastMicroop() const { return flags[IsLastMicroop]; }
 198     bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
 199     //This flag doesn't do anything yet
 200     bool isMicroBranch() const { return flags[IsMicroBranch]; }
 201     //@}
 202
 203     void setFirstMicroop() { flags[IsFirstMicroop] = true; }
 204     void setLastMicroop() { flags[IsLastMicroop] = true; }
 205     void setDelayedCommit() { flags[IsDelayedCommit] = true; }
 206     void setFlag(Flags f) { flags[f] = true; }
 207
 208     /// Operation class.  Used to select appropriate function unit in issue.
 209     OpClass opClass()     const { return _opClass; }
 210
 211
 212     /// Return logical index (architectural reg num) of i'th destination reg.
 213     /// Only the entries from 0 through numDestRegs()-1 are valid.
 214     const RegId& destRegIdx(int i) const { return _destRegIdx[i]; }
 215
 216     /// Return logical index (architectural reg num) of i'th source reg.
 217     /// Only the entries from 0 through numSrcRegs()-1 are valid.
 218     const RegId& srcRegIdx(int i)  const { return _srcRegIdx[i]; }
 219
 220     /// Pointer to a statically allocated "null" instruction object.
 221     static StaticInstPtr nullStaticInstPtr;
 222
 223     /// Pointer to a statically allocated generic "nop" instruction object.
 224     static StaticInstPtr nopStaticInstPtr;
 225
 226     /// The binary machine instruction.
 227     const ExtMachInst machInst;
 228
 229   protected:
 230
 231     /// See destRegIdx().
 232     RegId _destRegIdx[MaxInstDestRegs];
 233     /// See srcRegIdx().
 234     RegId _srcRegIdx[MaxInstSrcRegs];
 235
 236     /**
 237      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
 238      * methods.  Also useful to readily identify instructions from
 239      * within the debugger when #cachedDisassembly has not been
 240      * initialized.
 241      */
 242     const char *mnemonic;
 243
 244     /**
 245      * String representation of disassembly (lazily evaluated via
 246      * disassemble()).
 247      */
 248     mutable std::string *cachedDisassembly;
 249
 250     /**
 251      * Internal function to generate disassembly string.
 252      */
 253     virtual std::string
 254     generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 255
 256     /// Constructor.
 257     /// It's important to initialize everything here to a sane
 258     /// default, since the decoder generally only overrides
 259     /// the fields that are meaningful for the particular
 260     /// instruction.
 261     StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
 262         : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
 263           _numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0),
 264           _numVecDestRegs(0), _numVecElemDestRegs(0), _numVecPredDestRegs(0),
 265           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
 266     { }
 267
 268   public:
 269     virtual ~StaticInst();
 270
 271     virtual Fault execute(ExecContext *xc,
 272                           Trace::InstRecord *traceData) const = 0;
 273
 274     virtual Fault initiateAcc(ExecContext *xc,
 275                               Trace::InstRecord *traceData) const
 276     {
 277         panic("initiateAcc not defined!");
 278     }
 279
 280     virtual Fault completeAcc(Packet *pkt, ExecContext *xc,
 281                               Trace::InstRecord *traceData) const
 282     {
 283         panic("completeAcc not defined!");
 284     }
 285
 286     virtual void advancePC(TheISA::PCState &pcState) const = 0;
 287
 288     /**
 289      * Return the microop that goes with a particular micropc. This should
 290      * only be defined/used in macroops which will contain microops
 291      */
 292     virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
 293
 294     /**
 295      * Return the target address for a PC-relative branch.
 296      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
 297      * should be true).
 298      */
 299     virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
 300
 301     /**
 302      * Return the target address for an indirect branch (jump).  The
 303      * register value is read from the supplied thread context, so
 304      * the result is valid only if the thread context is about to
 305      * execute the branch in question.  Invalid if not an indirect
 306      * branch (i.e. isIndirectCtrl() should be true).
 307      */
 308     virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
 309
 310     /**
 311      * Return true if the instruction is a control transfer, and if so,
 312      * return the target address as well.
 313      */
 314     bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
 315                          TheISA::PCState &tgt) const;
 316
 317     /**
 318      * Return string representation of disassembled instruction.
 319      * The default version of this function will call the internal
 320      * virtual generateDisassembly() function to get the string,
 321      * then cache it in #cachedDisassembly.  If the disassembly
 322      * should not be cached, this function should be overridden directly.
 323      */
 324     virtual const std::string &disassemble(Addr pc,
 325         const SymbolTable *symtab = 0) const;
 326
 327     /**
 328      * Print a separator separated list of this instruction's set flag
 329      * names on the given stream.
 330      */
 331     void printFlags(std::ostream &outs, const std::string &separator) const;
 332
 333     /// Return name of machine instruction
 334     std::string getName() { return mnemonic; }
 335
 336   protected:
 337     template<typename T>
 338     size_t
 339     simpleAsBytes(void *buf, size_t max_size, const T &t)
 340     {
 341         size_t size = sizeof(T);
 342         if (size <= max_size)
 343             *reinterpret_cast<T *>(buf) = htole<T>(t);
 344         return size;
 345     }
 346
 347   public:
 348     /**
 349      * Instruction classes can override this function to return a
 350      * a representation of themselves as a blob of bytes, generally assumed to
 351      * be that instructions ExtMachInst.
 352      *
 353      * buf is a buffer to hold the bytes.
 354      * max_size is the size allocated for that buffer by the caller.
 355      * The return value is how much data was actually put into the buffer,
 356      * zero if no data was put in the buffer, or the necessary size of the
 357      * buffer if there wasn't enough space.
 358      */
 359     virtual size_t asBytes(void *buf, size_t max_size) { return 0; }
 360 };
 361
 362 #endif // __CPU_STATIC_INST_HH__