src/cpu/static_inst.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_STATIC_INST_HH__
  30 #define __CPU_STATIC_INST_HH__
  31
  32 #include <bitset>
  33 #include <string>
  34
  35 #include "base/hashmap.hh"
  36 #include "base/misc.hh"
  37 #include "base/refcnt.hh"
  38 #include "cpu/op_class.hh"
  39 #include "sim/host.hh"
  40 #include "arch/isa_traits.hh"
  41
  42 // forward declarations
  43 struct AlphaSimpleImpl;
  44 struct OzoneImpl;
  45 struct SimpleImpl;
  46 class ExecContext;
  47 class DynInst;
  48 class Packet;
  49
  50 template <class Impl>
  51 class AlphaDynInst;
  52
  53 template <class Impl>
  54 class OzoneDynInst;
  55
  56 class CheckerCPU;
  57 class FastCPU;
  58 class AtomicSimpleCPU;
  59 class TimingSimpleCPU;
  60 class InorderCPU;
  61 class SymbolTable;
  62
  63 namespace Trace {
  64     class InstRecord;
  65 }
  66
  67 /**
  68  * Base, ISA-independent static instruction class.
  69  *
  70  * The main component of this class is the vector of flags and the
  71  * associated methods for reading them.  Any object that can rely
  72  * solely on these flags can process instructions without being
  73  * recompiled for multiple ISAs.
  74  */
  75 class StaticInstBase : public RefCounted
  76 {
  77   protected:
  78
  79     /// Set of boolean static instruction properties.
  80     ///
  81     /// Notes:
  82     /// - The IsInteger and IsFloating flags are based on the class of
  83     /// registers accessed by the instruction.  Although most
  84     /// instructions will have exactly one of these two flags set, it
  85     /// is possible for an instruction to have neither (e.g., direct
  86     /// unconditional branches, memory barriers) or both (e.g., an
  87     /// FP/int conversion).
  88     /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
  89     /// will be set.
  90     /// - If IsControl is set, then exactly one of IsDirectControl or
  91     /// IsIndirect Control will be set, and exactly one of
  92     /// IsCondControl or IsUncondControl will be set.
  93     /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
  94     /// implemented as flags since in the current model there's no
  95     /// other way for instructions to inject behavior into the
  96     /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
  97     /// model we should be able to get rid of these flags and
  98     /// implement this behavior via the execute() methods.
  99     ///
 100     enum Flags {
 101         IsNop,          ///< Is a no-op (no effect at all).
 102
 103         IsInteger,      ///< References integer regs.
 104         IsFloating,     ///< References FP regs.
 105
 106         IsMemRef,       ///< References memory (load, store, or prefetch).
 107         IsLoad,         ///< Reads from memory (load or prefetch).
 108         IsStore,        ///< Writes to memory.
 109         IsStoreConditional,    ///< Store conditional instruction.
 110         IsInstPrefetch, ///< Instruction-cache prefetch.
 111         IsDataPrefetch, ///< Data-cache prefetch.
 112         IsCopy,         ///< Fast Cache block copy
 113
 114         IsControl,              ///< Control transfer instruction.
 115         IsDirectControl,        ///< PC relative control transfer.
 116         IsIndirectControl,      ///< Register indirect control transfer.
 117         IsCondControl,          ///< Conditional control transfer.
 118         IsUncondControl,        ///< Unconditional control transfer.
 119         IsCall,                 ///< Subroutine call.
 120         IsReturn,               ///< Subroutine return.
 121
 122         IsCondDelaySlot,///< Conditional Delay-Slot Instruction
 123
 124         IsThreadSync,   ///< Thread synchronization operation.
 125
 126         IsSerializing,  ///< Serializes pipeline: won't execute until all
 127                         /// older instructions have committed.
 128         IsSerializeBefore,
 129         IsSerializeAfter,
 130         IsMemBarrier,   ///< Is a memory barrier
 131         IsWriteBarrier, ///< Is a write barrier
 132
 133         IsNonSpeculative, ///< Should not be executed speculatively
 134         IsQuiesce,      ///< Is a quiesce instruction
 135
 136         IsIprAccess,    ///< Accesses IPRs
 137         IsUnverifiable, ///< Can't be verified by a checker
 138
 139         NumFlags
 140     };
 141
 142     /// Flag values for this instruction.
 143     std::bitset<NumFlags> flags;
 144
 145     /// See opClass().
 146     OpClass _opClass;
 147
 148     /// See numSrcRegs().
 149     int8_t _numSrcRegs;
 150
 151     /// See numDestRegs().
 152     int8_t _numDestRegs;
 153
 154     /// The following are used to track physical register usage
 155     /// for machines with separate int & FP reg files.
 156     //@{
 157     int8_t _numFPDestRegs;
 158     int8_t _numIntDestRegs;
 159     //@}
 160
 161     /// Constructor.
 162     /// It's important to initialize everything here to a sane
 163     /// default, since the decoder generally only overrides
 164     /// the fields that are meaningful for the particular
 165     /// instruction.
 166     StaticInstBase(OpClass __opClass)
 167         : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
 168           _numFPDestRegs(0), _numIntDestRegs(0)
 169     {
 170     }
 171
 172   public:
 173
 174     /// @name Register information.
 175     /// The sum of numFPDestRegs() and numIntDestRegs() equals
 176     /// numDestRegs().  The former two functions are used to track
 177     /// physical register usage for machines with separate int & FP
 178     /// reg files.
 179     //@{
 180     /// Number of source registers.
 181     int8_t numSrcRegs()  const { return _numSrcRegs; }
 182     /// Number of destination registers.
 183     int8_t numDestRegs() const { return _numDestRegs; }
 184     /// Number of floating-point destination regs.
 185     int8_t numFPDestRegs()  const { return _numFPDestRegs; }
 186     /// Number of integer destination regs.
 187     int8_t numIntDestRegs() const { return _numIntDestRegs; }
 188     //@}
 189
 190     /// @name Flag accessors.
 191     /// These functions are used to access the values of the various
 192     /// instruction property flags.  See StaticInstBase::Flags for descriptions
 193     /// of the individual flags.
 194     //@{
 195
 196     bool isNop()          const { return flags[IsNop]; }
 197
 198     bool isMemRef()       const { return flags[IsMemRef]; }
 199     bool isLoad()         const { return flags[IsLoad]; }
 200     bool isStore()        const { return flags[IsStore]; }
 201     bool isStoreConditional()     const { return flags[IsStoreConditional]; }
 202     bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
 203     bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
 204     bool isCopy()         const { return flags[IsCopy];}
 205
 206     bool isInteger()      const { return flags[IsInteger]; }
 207     bool isFloating()     const { return flags[IsFloating]; }
 208
 209     bool isControl()      const { return flags[IsControl]; }
 210     bool isCall()         const { return flags[IsCall]; }
 211     bool isReturn()       const { return flags[IsReturn]; }
 212     bool isDirectCtrl()   const { return flags[IsDirectControl]; }
 213     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
 214     bool isCondCtrl()     const { return flags[IsCondControl]; }
 215     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 216
 217     bool isThreadSync()   const { return flags[IsThreadSync]; }
 218     bool isSerializing()  const { return flags[IsSerializing] ||
 219                                       flags[IsSerializeBefore] ||
 220                                       flags[IsSerializeAfter]; }
 221     bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
 222     bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
 223     bool isMemBarrier()   const { return flags[IsMemBarrier]; }
 224     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
 225     bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
 226     bool isQuiesce() const { return flags[IsQuiesce]; }
 227     bool isIprAccess() const { return flags[IsIprAccess]; }
 228     bool isUnverifiable() const { return flags[IsUnverifiable]; }
 229     //@}
 230
 231     /// Operation class.  Used to select appropriate function unit in issue.
 232     OpClass opClass()     const { return _opClass; }
 233 };
 234
 235
 236 // forward declaration
 237 class StaticInstPtr;
 238
 239 /**
 240  * Generic yet ISA-dependent static instruction class.
 241  *
 242  * This class builds on StaticInstBase, defining fields and interfaces
 243  * that are generic across all ISAs but that differ in details
 244  * according to the specific ISA being used.
 245  */
 246 class StaticInst : public StaticInstBase
 247 {
 248   public:
 249
 250     /// Binary machine instruction type.
 251     typedef TheISA::MachInst MachInst;
 252     /// Binary extended machine instruction type.
 253     typedef TheISA::ExtMachInst ExtMachInst;
 254     /// Logical register index type.
 255     typedef TheISA::RegIndex RegIndex;
 256
 257     enum {
 258         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
 259         MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
 260     };
 261
 262
 263     /// Return logical index (architectural reg num) of i'th destination reg.
 264     /// Only the entries from 0 through numDestRegs()-1 are valid.
 265     RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
 266
 267     /// Return logical index (architectural reg num) of i'th source reg.
 268     /// Only the entries from 0 through numSrcRegs()-1 are valid.
 269     RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
 270
 271     /// Pointer to a statically allocated "null" instruction object.
 272     /// Used to give eaCompInst() and memAccInst() something to return
 273     /// when called on non-memory instructions.
 274     static StaticInstPtr nullStaticInstPtr;
 275
 276     /**
 277      * Memory references only: returns "fake" instruction representing
 278      * the effective address part of the memory operation.  Used to
 279      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 280      * just the EA computation.
 281      */
 282     virtual const
 283     StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
 284
 285     /**
 286      * Memory references only: returns "fake" instruction representing
 287      * the memory access part of the memory operation.  Used to
 288      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 289      * just the memory access (not the EA computation).
 290      */
 291     virtual const
 292     StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
 293
 294     /// The binary machine instruction.
 295     const ExtMachInst machInst;
 296
 297   protected:
 298
 299     /// See destRegIdx().
 300     RegIndex _destRegIdx[MaxInstDestRegs];
 301     /// See srcRegIdx().
 302     RegIndex _srcRegIdx[MaxInstSrcRegs];
 303
 304     /**
 305      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
 306      * methods.  Also useful to readily identify instructions from
 307      * within the debugger when #cachedDisassembly has not been
 308      * initialized.
 309      */
 310     const char *mnemonic;
 311
 312     /**
 313      * String representation of disassembly (lazily evaluated via
 314      * disassemble()).
 315      */
 316     mutable std::string *cachedDisassembly;
 317
 318     /**
 319      * Internal function to generate disassembly string.
 320      */
 321     virtual std::string
 322     generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 323
 324     /// Constructor.
 325     StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
 326         : StaticInstBase(__opClass),
 327           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
 328     {
 329     }
 330
 331   public:
 332
 333     virtual ~StaticInst()
 334     {
 335         if (cachedDisassembly)
 336             delete cachedDisassembly;
 337     }
 338
 339 /**
 340  * The execute() signatures are auto-generated by scons based on the
 341  * set of CPU models we are compiling in today.
 342  */
 343 #include "cpu/static_inst_exec_sigs.hh"
 344
 345     /**
 346      * Return the target address for a PC-relative branch.
 347      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
 348      * should be true).
 349      */
 350     virtual Addr branchTarget(Addr branchPC) const
 351     {
 352         panic("StaticInst::branchTarget() called on instruction "
 353               "that is not a PC-relative branch.");
 354     }
 355
 356     /**
 357      * Return the target address for an indirect branch (jump).  The
 358      * register value is read from the supplied execution context, so
 359      * the result is valid only if the execution context is about to
 360      * execute the branch in question.  Invalid if not an indirect
 361      * branch (i.e. isIndirectCtrl() should be true).
 362      */
 363     virtual Addr branchTarget(ExecContext *xc) const
 364     {
 365         panic("StaticInst::branchTarget() called on instruction "
 366               "that is not an indirect branch.");
 367     }
 368
 369     /**
 370      * Return true if the instruction is a control transfer, and if so,
 371      * return the target address as well.
 372      */
 373     bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
 374
 375     /**
 376      * Return string representation of disassembled instruction.
 377      * The default version of this function will call the internal
 378      * virtual generateDisassembly() function to get the string,
 379      * then cache it in #cachedDisassembly.  If the disassembly
 380      * should not be cached, this function should be overridden directly.
 381      */
 382     virtual const std::string &disassemble(Addr pc,
 383                                            const SymbolTable *symtab = 0) const
 384     {
 385         if (!cachedDisassembly)
 386             cachedDisassembly =
 387                 new std::string(generateDisassembly(pc, symtab));
 388
 389         return *cachedDisassembly;
 390     }
 391
 392     /// Decoded instruction cache type.
 393     /// For now we're using a generic hash_map; this seems to work
 394     /// pretty well.
 395     typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
 396
 397     /// A cache of decoded instruction objects.
 398     static DecodeCache decodeCache;
 399
 400     /**
 401      * Dump some basic stats on the decode cache hash map.
 402      * Only gets called if DECODE_CACHE_HASH_STATS is defined.
 403      */
 404     static void dumpDecodeCacheStats();
 405
 406     /// Decode a machine instruction.
 407     /// @param mach_inst The binary instruction to decode.
 408     /// @retval A pointer to the corresponding StaticInst object.
 409     //This is defined as inline below.
 410     static StaticInstPtr decode(ExtMachInst mach_inst);
 411
 412     //MIPS Decoder Debug Functions
 413     int getOpcode() { return (machInst & 0xFC000000) >> 26 ; }//31..26
 414     int getRs() {     return (machInst & 0x03E00000) >> 21; }    //25...21
 415     int getRt() {     return (machInst & 0x001F0000) >> 16;  }    //20...16
 416     int getRd() {     return (machInst & 0x0000F800) >> 11; }    //15...11
 417     int getImm() {  return (machInst & 0x0000FFFF); }    //15...0
 418     int getFunction(){  return (machInst & 0x0000003F); }//5...0
 419     int getBranch(){  return (machInst & 0x0000FFFF); }//15...0
 420     int getJump(){    return (machInst & 0x03FFFFFF); }//5...0
 421     int getHint(){    return (machInst & 0x000007C0) >> 6; }  //10...6
 422     std::string getName() { return mnemonic; }
 423 };
 424
 425 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
 426
 427 /// Reference-counted pointer to a StaticInst object.
 428 /// This type should be used instead of "StaticInst *" so that
 429 /// StaticInst objects can be properly reference-counted.
 430 class StaticInstPtr : public RefCountingPtr<StaticInst>
 431 {
 432   public:
 433     /// Constructor.
 434     StaticInstPtr()
 435         : RefCountingPtr<StaticInst>()
 436     {
 437     }
 438
 439     /// Conversion from "StaticInst *".
 440     StaticInstPtr(StaticInst *p)
 441         : RefCountingPtr<StaticInst>(p)
 442     {
 443     }
 444
 445     /// Copy constructor.
 446     StaticInstPtr(const StaticInstPtr &r)
 447         : RefCountingPtr<StaticInst>(r)
 448     {
 449     }
 450
 451     /// Construct directly from machine instruction.
 452     /// Calls StaticInst::decode().
 453     StaticInstPtr(TheISA::ExtMachInst mach_inst)
 454         : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
 455     {
 456     }
 457
 458     /// Convert to pointer to StaticInstBase class.
 459     operator const StaticInstBasePtr()
 460     {
 461         return this->get();
 462     }
 463 };
 464
 465 inline StaticInstPtr
 466 StaticInst::decode(StaticInst::ExtMachInst mach_inst)
 467 {
 468 #ifdef DECODE_CACHE_HASH_STATS
 469     // Simple stats on decode hash_map.  Turns out the default
 470     // hash function is as good as anything I could come up with.
 471     const int dump_every_n = 10000000;
 472     static int decodes_til_dump = dump_every_n;
 473
 474     if (--decodes_til_dump == 0) {
 475         dumpDecodeCacheStats();
 476         decodes_til_dump = dump_every_n;
 477     }
 478 #endif
 479
 480     DecodeCache::iterator iter = decodeCache.find(mach_inst);
 481     if (iter != decodeCache.end()) {
 482         return iter->second;
 483     }
 484
 485     StaticInstPtr si = TheISA::decodeInst(mach_inst);
 486     decodeCache[mach_inst] = si;
 487     return si;
 488 }
 489
 490 #endif // __CPU_STATIC_INST_HH__