src/cpu/static_inst.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #ifndef __CPU_STATIC_INST_HH__
  32 #define __CPU_STATIC_INST_HH__
  33
  34 #include <bitset>
  35 #include <string>
  36
  37 #include "arch/isa_traits.hh"
  38 #include "arch/utility.hh"
  39 #include "sim/faults.hh"
  40 #include "base/bitfield.hh"
  41 #include "base/hashmap.hh"
  42 #include "base/misc.hh"
  43 #include "base/refcnt.hh"
  44 #include "cpu/op_class.hh"
  45 #include "cpu/o3/dyn_inst.hh"
  46 #include "sim/faults.hh"
  47 #include "sim/host.hh"
  48
  49 // forward declarations
  50 struct AlphaSimpleImpl;
  51 struct OzoneImpl;
  52 struct SimpleImpl;
  53 class ThreadContext;
  54 class DynInst;
  55 class Packet;
  56
  57 template <class Impl>
  58 class OzoneDynInst;
  59
  60 class CheckerCPU;
  61 class FastCPU;
  62 class AtomicSimpleCPU;
  63 class TimingSimpleCPU;
  64 class InorderCPU;
  65 class SymbolTable;
  66 class AddrDecodePage;
  67
  68 namespace Trace {
  69     class InstRecord;
  70 }
  71
  72 typedef uint32_t MicroPC;
  73
  74 /**
  75  * Base, ISA-independent static instruction class.
  76  *
  77  * The main component of this class is the vector of flags and the
  78  * associated methods for reading them.  Any object that can rely
  79  * solely on these flags can process instructions without being
  80  * recompiled for multiple ISAs.
  81  */
  82 class StaticInstBase : public RefCounted
  83 {
  84   protected:
  85
  86     /// Set of boolean static instruction properties.
  87     ///
  88     /// Notes:
  89     /// - The IsInteger and IsFloating flags are based on the class of
  90     /// registers accessed by the instruction.  Although most
  91     /// instructions will have exactly one of these two flags set, it
  92     /// is possible for an instruction to have neither (e.g., direct
  93     /// unconditional branches, memory barriers) or both (e.g., an
  94     /// FP/int conversion).
  95     /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
  96     /// will be set.
  97     /// - If IsControl is set, then exactly one of IsDirectControl or
  98     /// IsIndirect Control will be set, and exactly one of
  99     /// IsCondControl or IsUncondControl will be set.
 100     /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
 101     /// implemented as flags since in the current model there's no
 102     /// other way for instructions to inject behavior into the
 103     /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
 104     /// model we should be able to get rid of these flags and
 105     /// implement this behavior via the execute() methods.
 106     ///
 107     enum Flags {
 108         IsNop,          ///< Is a no-op (no effect at all).
 109
 110         IsInteger,      ///< References integer regs.
 111         IsFloating,     ///< References FP regs.
 112
 113         IsMemRef,       ///< References memory (load, store, or prefetch).
 114         IsLoad,         ///< Reads from memory (load or prefetch).
 115         IsStore,        ///< Writes to memory.
 116         IsStoreConditional,    ///< Store conditional instruction.
 117         IsInstPrefetch, ///< Instruction-cache prefetch.
 118         IsDataPrefetch, ///< Data-cache prefetch.
 119         IsCopy,         ///< Fast Cache block copy
 120
 121         IsControl,              ///< Control transfer instruction.
 122         IsDirectControl,        ///< PC relative control transfer.
 123         IsIndirectControl,      ///< Register indirect control transfer.
 124         IsCondControl,          ///< Conditional control transfer.
 125         IsUncondControl,        ///< Unconditional control transfer.
 126         IsCall,                 ///< Subroutine call.
 127         IsReturn,               ///< Subroutine return.
 128
 129         IsCondDelaySlot,///< Conditional Delay-Slot Instruction
 130
 131         IsThreadSync,   ///< Thread synchronization operation.
 132
 133         IsSerializing,  ///< Serializes pipeline: won't execute until all
 134                         /// older instructions have committed.
 135         IsSerializeBefore,
 136         IsSerializeAfter,
 137         IsMemBarrier,   ///< Is a memory barrier
 138         IsWriteBarrier, ///< Is a write barrier
 139
 140         IsNonSpeculative, ///< Should not be executed speculatively
 141         IsQuiesce,      ///< Is a quiesce instruction
 142
 143         IsIprAccess,    ///< Accesses IPRs
 144         IsUnverifiable, ///< Can't be verified by a checker
 145
 146         IsSyscall,      ///< Causes a system call to be emulated in syscall
 147                         /// emulation mode.
 148
 149         //Flags for microcode
 150         IsMacroop,      ///< Is a macroop containing microops
 151         IsMicroop,      ///< Is a microop
 152         IsDelayedCommit,        ///< This microop doesn't commit right away
 153         IsLastMicroop,  ///< This microop ends a microop sequence
 154         IsFirstMicroop, ///< This microop begins a microop sequence
 155         //This flag doesn't do anything yet
 156         IsMicroBranch,  ///< This microop branches within the microcode for a macroop
 157
 158         NumFlags
 159     };
 160
 161     /// Flag values for this instruction.
 162     std::bitset<NumFlags> flags;
 163
 164     /// See opClass().
 165     OpClass _opClass;
 166
 167     /// See numSrcRegs().
 168     int8_t _numSrcRegs;
 169
 170     /// See numDestRegs().
 171     int8_t _numDestRegs;
 172
 173     /// The following are used to track physical register usage
 174     /// for machines with separate int & FP reg files.
 175     //@{
 176     int8_t _numFPDestRegs;
 177     int8_t _numIntDestRegs;
 178     //@}
 179
 180     /// Constructor.
 181     /// It's important to initialize everything here to a sane
 182     /// default, since the decoder generally only overrides
 183     /// the fields that are meaningful for the particular
 184     /// instruction.
 185     StaticInstBase(OpClass __opClass)
 186         : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
 187           _numFPDestRegs(0), _numIntDestRegs(0)
 188     {
 189     }
 190
 191   public:
 192
 193     /// @name Register information.
 194     /// The sum of numFPDestRegs() and numIntDestRegs() equals
 195     /// numDestRegs().  The former two functions are used to track
 196     /// physical register usage for machines with separate int & FP
 197     /// reg files.
 198     //@{
 199     /// Number of source registers.
 200     int8_t numSrcRegs()  const { return _numSrcRegs; }
 201     /// Number of destination registers.
 202     int8_t numDestRegs() const { return _numDestRegs; }
 203     /// Number of floating-point destination regs.
 204     int8_t numFPDestRegs()  const { return _numFPDestRegs; }
 205     /// Number of integer destination regs.
 206     int8_t numIntDestRegs() const { return _numIntDestRegs; }
 207     //@}
 208
 209     /// @name Flag accessors.
 210     /// These functions are used to access the values of the various
 211     /// instruction property flags.  See StaticInstBase::Flags for descriptions
 212     /// of the individual flags.
 213     //@{
 214
 215     bool isNop()          const { return flags[IsNop]; }
 216
 217     bool isMemRef()       const { return flags[IsMemRef]; }
 218     bool isLoad()         const { return flags[IsLoad]; }
 219     bool isStore()        const { return flags[IsStore]; }
 220     bool isStoreConditional()     const { return flags[IsStoreConditional]; }
 221     bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
 222     bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
 223     bool isCopy()         const { return flags[IsCopy];}
 224
 225     bool isInteger()      const { return flags[IsInteger]; }
 226     bool isFloating()     const { return flags[IsFloating]; }
 227
 228     bool isControl()      const { return flags[IsControl]; }
 229     bool isCall()         const { return flags[IsCall]; }
 230     bool isReturn()       const { return flags[IsReturn]; }
 231     bool isDirectCtrl()   const { return flags[IsDirectControl]; }
 232     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
 233     bool isCondCtrl()     const { return flags[IsCondControl]; }
 234     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 235     bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
 236
 237     bool isThreadSync()   const { return flags[IsThreadSync]; }
 238     bool isSerializing()  const { return flags[IsSerializing] ||
 239                                       flags[IsSerializeBefore] ||
 240                                       flags[IsSerializeAfter]; }
 241     bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
 242     bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
 243     bool isMemBarrier()   const { return flags[IsMemBarrier]; }
 244     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
 245     bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
 246     bool isQuiesce() const { return flags[IsQuiesce]; }
 247     bool isIprAccess() const { return flags[IsIprAccess]; }
 248     bool isUnverifiable() const { return flags[IsUnverifiable]; }
 249     bool isSyscall() const { return flags[IsSyscall]; }
 250     bool isMacroop() const { return flags[IsMacroop]; }
 251     bool isMicroop() const { return flags[IsMicroop]; }
 252     bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
 253     bool isLastMicroop() const { return flags[IsLastMicroop]; }
 254     bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
 255     //This flag doesn't do anything yet
 256     bool isMicroBranch() const { return flags[IsMicroBranch]; }
 257     //@}
 258
 259     /// Operation class.  Used to select appropriate function unit in issue.
 260     OpClass opClass()     const { return _opClass; }
 261 };
 262
 263
 264 // forward declaration
 265 class StaticInstPtr;
 266
 267 /**
 268  * Generic yet ISA-dependent static instruction class.
 269  *
 270  * This class builds on StaticInstBase, defining fields and interfaces
 271  * that are generic across all ISAs but that differ in details
 272  * according to the specific ISA being used.
 273  */
 274 class StaticInst : public StaticInstBase
 275 {
 276   public:
 277
 278     /// Binary machine instruction type.
 279     typedef TheISA::MachInst MachInst;
 280     /// Binary extended machine instruction type.
 281     typedef TheISA::ExtMachInst ExtMachInst;
 282     /// Logical register index type.
 283     typedef TheISA::RegIndex RegIndex;
 284
 285     enum {
 286         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
 287         MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
 288     };
 289
 290
 291     /// Return logical index (architectural reg num) of i'th destination reg.
 292     /// Only the entries from 0 through numDestRegs()-1 are valid.
 293     RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
 294
 295     /// Return logical index (architectural reg num) of i'th source reg.
 296     /// Only the entries from 0 through numSrcRegs()-1 are valid.
 297     RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
 298
 299     /// Pointer to a statically allocated "null" instruction object.
 300     /// Used to give eaCompInst() and memAccInst() something to return
 301     /// when called on non-memory instructions.
 302     static StaticInstPtr nullStaticInstPtr;
 303
 304     /**
 305      * Memory references only: returns "fake" instruction representing
 306      * the effective address part of the memory operation.  Used to
 307      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 308      * just the EA computation.
 309      */
 310     virtual const
 311     StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
 312
 313     /**
 314      * Memory references only: returns "fake" instruction representing
 315      * the memory access part of the memory operation.  Used to
 316      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 317      * just the memory access (not the EA computation).
 318      */
 319     virtual const
 320     StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
 321
 322     /// The binary machine instruction.
 323     const ExtMachInst machInst;
 324
 325   protected:
 326
 327     /// See destRegIdx().
 328     RegIndex _destRegIdx[MaxInstDestRegs];
 329     /// See srcRegIdx().
 330     RegIndex _srcRegIdx[MaxInstSrcRegs];
 331
 332     /**
 333      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
 334      * methods.  Also useful to readily identify instructions from
 335      * within the debugger when #cachedDisassembly has not been
 336      * initialized.
 337      */
 338     const char *mnemonic;
 339
 340     /**
 341      * String representation of disassembly (lazily evaluated via
 342      * disassemble()).
 343      */
 344     mutable std::string *cachedDisassembly;
 345
 346     /**
 347      * Internal function to generate disassembly string.
 348      */
 349     virtual std::string
 350     generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 351
 352     /// Constructor.
 353     StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
 354         : StaticInstBase(__opClass),
 355           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
 356     {
 357         memset(&recentDecodes, 0, 2 * sizeof(cacheElement));
 358     }
 359
 360   public:
 361
 362     virtual ~StaticInst()
 363     {
 364         if (cachedDisassembly)
 365             delete cachedDisassembly;
 366     }
 367
 368 /**
 369  * The execute() signatures are auto-generated by scons based on the
 370  * set of CPU models we are compiling in today.
 371  */
 372 #include "cpu/static_inst_exec_sigs.hh"
 373
 374     /**
 375      * Return the microop that goes with a particular micropc. This should
 376      * only be defined/used in macroops which will contain microops
 377      */
 378     virtual StaticInstPtr fetchMicroop(MicroPC micropc);
 379
 380     /**
 381      * Return the target address for a PC-relative branch.
 382      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
 383      * should be true).
 384      */
 385     virtual Addr branchTarget(Addr branchPC) const
 386     {
 387         panic("StaticInst::branchTarget() called on instruction "
 388               "that is not a PC-relative branch.");
 389         M5_DUMMY_RETURN
 390     }
 391
 392     /**
 393      * Return the target address for an indirect branch (jump).  The
 394      * register value is read from the supplied thread context, so
 395      * the result is valid only if the thread context is about to
 396      * execute the branch in question.  Invalid if not an indirect
 397      * branch (i.e. isIndirectCtrl() should be true).
 398      */
 399     virtual Addr branchTarget(ThreadContext *tc) const
 400     {
 401         panic("StaticInst::branchTarget() called on instruction "
 402               "that is not an indirect branch.");
 403     }
 404         M5_DUMMY_RETURN
 405
 406     /**
 407      * Return true if the instruction is a control transfer, and if so,
 408      * return the target address as well.
 409      */
 410     bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
 411
 412     /**
 413      * Return string representation of disassembled instruction.
 414      * The default version of this function will call the internal
 415      * virtual generateDisassembly() function to get the string,
 416      * then cache it in #cachedDisassembly.  If the disassembly
 417      * should not be cached, this function should be overridden directly.
 418      */
 419     virtual const std::string &disassemble(Addr pc,
 420                                            const SymbolTable *symtab = 0) const
 421     {
 422         if (!cachedDisassembly)
 423             cachedDisassembly =
 424                 new std::string(generateDisassembly(pc, symtab));
 425
 426         return *cachedDisassembly;
 427     }
 428
 429     /// Decoded instruction cache type.
 430     /// For now we're using a generic hash_map; this seems to work
 431     /// pretty well.
 432     typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
 433
 434     /// A cache of decoded instruction objects.
 435     static DecodeCache decodeCache;
 436
 437     /**
 438      * Dump some basic stats on the decode cache hash map.
 439      * Only gets called if DECODE_CACHE_HASH_STATS is defined.
 440      */
 441     static void dumpDecodeCacheStats();
 442
 443     /// Decode a machine instruction.
 444     /// @param mach_inst The binary instruction to decode.
 445     /// @retval A pointer to the corresponding StaticInst object.
 446     //This is defined as inlined below.
 447     static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
 448
 449     /// Return name of machine instruction
 450     std::string getName() { return mnemonic; }
 451
 452     /// Decoded instruction cache type, for address decoding.
 453     /// A generic hash_map is used.
 454     typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache;
 455
 456     /// A cache of decoded instruction objects from addresses.
 457     static AddrDecodeCache addrDecodeCache;
 458
 459     struct cacheElement {
 460         Addr page_addr;
 461         AddrDecodePage *decodePage;
 462     } ;
 463
 464     /// An array of recently decoded instructions.
 465     // might not use an array if there is only two elements
 466     static struct cacheElement recentDecodes[2];
 467
 468     /// Updates the recently decoded instructions entries
 469     /// @param page_addr The page address recently used.
 470     /// @param decodePage Pointer to decoding page containing the decoded
 471     ///                   instruction.
 472     static inline void
 473     updateCache(Addr page_addr, AddrDecodePage *decodePage)
 474     {
 475         recentDecodes[1].page_addr = recentDecodes[0].page_addr;
 476         recentDecodes[1].decodePage = recentDecodes[0].decodePage;
 477         recentDecodes[0].page_addr = page_addr;
 478         recentDecodes[0].decodePage = decodePage;
 479     }
 480
 481     /// Searches the decoded instruction cache for instruction decoding.
 482     /// If it is not found, then we decode the instruction.
 483     /// Otherwise, we get the instruction from the cache and move it into
 484     /// the address-to-instruction decoding page.
 485     /// @param mach_inst The binary instruction to decode.
 486     /// @param addr The address that contained the binary instruction.
 487     /// @param decodePage Pointer to decoding page containing the instruction.
 488     /// @retval A pointer to the corresponding StaticInst object.
 489     //This is defined as inlined below.
 490     static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr,
 491                                      AddrDecodePage * decodePage);
 492 };
 493
 494 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
 495
 496 /// Reference-counted pointer to a StaticInst object.
 497 /// This type should be used instead of "StaticInst *" so that
 498 /// StaticInst objects can be properly reference-counted.
 499 class StaticInstPtr : public RefCountingPtr<StaticInst>
 500 {
 501   public:
 502     /// Constructor.
 503     StaticInstPtr()
 504         : RefCountingPtr<StaticInst>()
 505     {
 506     }
 507
 508     /// Conversion from "StaticInst *".
 509     StaticInstPtr(StaticInst *p)
 510         : RefCountingPtr<StaticInst>(p)
 511     {
 512     }
 513
 514     /// Copy constructor.
 515     StaticInstPtr(const StaticInstPtr &r)
 516         : RefCountingPtr<StaticInst>(r)
 517     {
 518     }
 519
 520     /// Construct directly from machine instruction.
 521     /// Calls StaticInst::decode().
 522     explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr)
 523         : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr))
 524     {
 525     }
 526
 527     /// Convert to pointer to StaticInstBase class.
 528     operator const StaticInstBasePtr()
 529     {
 530         return this->get();
 531     }
 532 };
 533
 534 /// A page of a list of decoded instructions from an address.
 535 class AddrDecodePage
 536 {
 537   typedef TheISA::ExtMachInst ExtMachInst;
 538   protected:
 539     StaticInstPtr instructions[TheISA::PageBytes];
 540     bool valid[TheISA::PageBytes];
 541     Addr lowerMask;
 542
 543   public:
 544     /// Constructor
 545     AddrDecodePage() {
 546         lowerMask = TheISA::PageBytes - 1;
 547         memset(valid, 0, TheISA::PageBytes);
 548     }
 549
 550     /// Checks if the instruction is already decoded and the machine
 551     /// instruction in the cache matches the current machine instruction
 552     /// related to the address
 553     /// @param mach_inst The binary instruction to check
 554     /// @param addr The address containing the instruction
 555     inline bool decoded(ExtMachInst mach_inst, Addr addr)
 556     {
 557         return (valid[addr & lowerMask] &&
 558                 (instructions[addr & lowerMask]->machInst == mach_inst));
 559     }
 560
 561     /// Returns the instruction object. decoded should be called first
 562     /// to check if the instruction is valid.
 563     /// @param addr The address of the instruction.
 564     /// @retval A pointer to the corresponding StaticInst object.
 565     inline StaticInstPtr getInst(Addr addr)
 566     {   return instructions[addr & lowerMask]; }
 567
 568     /// Inserts a pointer to a StaticInst object into the list of decoded
 569     /// instructions on the page.
 570     /// @param addr The address of the instruction.
 571     /// @param si A pointer to the corresponding StaticInst object.
 572     inline void insert(Addr addr, StaticInstPtr &si)
 573     {
 574         instructions[addr & lowerMask] = si;
 575         valid[addr & lowerMask] = true;
 576     }
 577
 578 };
 579
 580
 581 inline StaticInstPtr
 582 StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
 583 {
 584 #ifdef DECODE_CACHE_HASH_STATS
 585     // Simple stats on decode hash_map.  Turns out the default
 586     // hash function is as good as anything I could come up with.
 587     const int dump_every_n = 10000000;
 588     static int decodes_til_dump = dump_every_n;
 589
 590     if (--decodes_til_dump == 0) {
 591         dumpDecodeCacheStats();
 592         decodes_til_dump = dump_every_n;
 593     }
 594 #endif
 595
 596     Addr page_addr = addr & ~(TheISA::PageBytes - 1);
 597
 598     // checks recently decoded addresses
 599     if (recentDecodes[0].decodePage &&
 600         page_addr == recentDecodes[0].page_addr) {
 601         if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
 602             return recentDecodes[0].decodePage->getInst(addr);
 603
 604         return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
 605     }
 606
 607     if (recentDecodes[1].decodePage &&
 608         page_addr == recentDecodes[1].page_addr) {
 609         if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
 610             return recentDecodes[1].decodePage->getInst(addr);
 611
 612         return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
 613     }
 614
 615     // searches the page containing the address to decode
 616     AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr);
 617     if (iter != addrDecodeCache.end()) {
 618         updateCache(page_addr, iter->second);
 619         if (iter->second->decoded(mach_inst, addr))
 620             return iter->second->getInst(addr);
 621
 622         return searchCache(mach_inst, addr, iter->second);
 623     }
 624
 625     // creates a new object for a page of decoded instructions
 626     AddrDecodePage * decodePage = new AddrDecodePage;
 627     addrDecodeCache[page_addr] = decodePage;
 628     updateCache(page_addr, decodePage);
 629     return searchCache(mach_inst, addr, decodePage);
 630 }
 631
 632 inline StaticInstPtr
 633 StaticInst::searchCache(ExtMachInst mach_inst, Addr addr,
 634                         AddrDecodePage * decodePage)
 635 {
 636     DecodeCache::iterator iter = decodeCache.find(mach_inst);
 637     if (iter != decodeCache.end()) {
 638         decodePage->insert(addr, iter->second);
 639         return iter->second;
 640     }
 641
 642     StaticInstPtr si = TheISA::decodeInst(mach_inst);
 643     decodePage->insert(addr, si);
 644     decodeCache[mach_inst] = si;
 645     return si;
 646 }
 647
 648 #endif // __CPU_STATIC_INST_HH__