src/cpu/static_inst.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #ifndef __CPU_STATIC_INST_HH__
  32 #define __CPU_STATIC_INST_HH__
  33
  34 #include <bitset>
  35 #include <string>
  36
  37 #include "arch/isa_traits.hh"
  38 #include "arch/types.hh"
  39 #include "arch/registers.hh"
  40 #include "config/the_isa.hh"
  41 #include "base/hashmap.hh"
  42 #include "base/misc.hh"
  43 #include "base/refcnt.hh"
  44 #include "base/types.hh"
  45 #include "cpu/op_class.hh"
  46 #include "sim/fault.hh"
  47
  48 // forward declarations
  49 struct AlphaSimpleImpl;
  50 struct OzoneImpl;
  51 struct SimpleImpl;
  52 class ThreadContext;
  53 class DynInst;
  54 class Packet;
  55
  56 class O3CPUImpl;
  57 template <class Impl> class BaseO3DynInst;
  58 typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
  59 template <class Impl> class OzoneDynInst;
  60 class InOrderDynInst;
  61
  62 class CheckerCPU;
  63 class FastCPU;
  64 class AtomicSimpleCPU;
  65 class TimingSimpleCPU;
  66 class InorderCPU;
  67 class SymbolTable;
  68 class AddrDecodePage;
  69
  70 namespace Trace {
  71     class InstRecord;
  72 }
  73
  74 /**
  75  * Base, ISA-independent static instruction class.
  76  *
  77  * The main component of this class is the vector of flags and the
  78  * associated methods for reading them.  Any object that can rely
  79  * solely on these flags can process instructions without being
  80  * recompiled for multiple ISAs.
  81  */
  82 class StaticInstBase : public RefCounted
  83 {
  84   public:
  85
  86     /// Set of boolean static instruction properties.
  87     ///
  88     /// Notes:
  89     /// - The IsInteger and IsFloating flags are based on the class of
  90     /// registers accessed by the instruction.  Although most
  91     /// instructions will have exactly one of these two flags set, it
  92     /// is possible for an instruction to have neither (e.g., direct
  93     /// unconditional branches, memory barriers) or both (e.g., an
  94     /// FP/int conversion).
  95     /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
  96     /// will be set.
  97     /// - If IsControl is set, then exactly one of IsDirectControl or
  98     /// IsIndirect Control will be set, and exactly one of
  99     /// IsCondControl or IsUncondControl will be set.
 100     /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
 101     /// implemented as flags since in the current model there's no
 102     /// other way for instructions to inject behavior into the
 103     /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
 104     /// model we should be able to get rid of these flags and
 105     /// implement this behavior via the execute() methods.
 106     ///
 107     enum Flags {
 108         IsNop,          ///< Is a no-op (no effect at all).
 109
 110         IsInteger,      ///< References integer regs.
 111         IsFloating,     ///< References FP regs.
 112
 113         IsMemRef,       ///< References memory (load, store, or prefetch).
 114         IsLoad,         ///< Reads from memory (load or prefetch).
 115         IsStore,        ///< Writes to memory.
 116         IsStoreConditional,    ///< Store conditional instruction.
 117         IsIndexed,      ///< Accesses memory with an indexed address computation
 118         IsInstPrefetch, ///< Instruction-cache prefetch.
 119         IsDataPrefetch, ///< Data-cache prefetch.
 120         IsCopy,         ///< Fast Cache block copy
 121
 122         IsControl,              ///< Control transfer instruction.
 123         IsDirectControl,        ///< PC relative control transfer.
 124         IsIndirectControl,      ///< Register indirect control transfer.
 125         IsCondControl,          ///< Conditional control transfer.
 126         IsUncondControl,        ///< Unconditional control transfer.
 127         IsCall,                 ///< Subroutine call.
 128         IsReturn,               ///< Subroutine return.
 129
 130         IsCondDelaySlot,///< Conditional Delay-Slot Instruction
 131
 132         IsThreadSync,   ///< Thread synchronization operation.
 133
 134         IsSerializing,  ///< Serializes pipeline: won't execute until all
 135                         /// older instructions have committed.
 136         IsSerializeBefore,
 137         IsSerializeAfter,
 138         IsMemBarrier,   ///< Is a memory barrier
 139         IsWriteBarrier, ///< Is a write barrier
 140         IsReadBarrier,  ///< Is a read barrier
 141         IsERET, /// <- Causes the IFU to stall (MIPS ISA)
 142
 143         IsNonSpeculative, ///< Should not be executed speculatively
 144         IsQuiesce,      ///< Is a quiesce instruction
 145
 146         IsIprAccess,    ///< Accesses IPRs
 147         IsUnverifiable, ///< Can't be verified by a checker
 148
 149         IsSyscall,      ///< Causes a system call to be emulated in syscall
 150                         /// emulation mode.
 151
 152         //Flags for microcode
 153         IsMacroop,      ///< Is a macroop containing microops
 154         IsMicroop,      ///< Is a microop
 155         IsDelayedCommit,        ///< This microop doesn't commit right away
 156         IsLastMicroop,  ///< This microop ends a microop sequence
 157         IsFirstMicroop, ///< This microop begins a microop sequence
 158         //This flag doesn't do anything yet
 159         IsMicroBranch,  ///< This microop branches within the microcode for a macroop
 160         IsDspOp,
 161
 162         NumFlags
 163     };
 164
 165   protected:
 166
 167     /// Flag values for this instruction.
 168     std::bitset<NumFlags> flags;
 169
 170     /// See opClass().
 171     OpClass _opClass;
 172
 173     /// See numSrcRegs().
 174     int8_t _numSrcRegs;
 175
 176     /// See numDestRegs().
 177     int8_t _numDestRegs;
 178
 179     /// The following are used to track physical register usage
 180     /// for machines with separate int & FP reg files.
 181     //@{
 182     int8_t _numFPDestRegs;
 183     int8_t _numIntDestRegs;
 184     //@}
 185
 186     /// Constructor.
 187     /// It's important to initialize everything here to a sane
 188     /// default, since the decoder generally only overrides
 189     /// the fields that are meaningful for the particular
 190     /// instruction.
 191     StaticInstBase(OpClass __opClass)
 192         : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
 193           _numFPDestRegs(0), _numIntDestRegs(0)
 194     {
 195     }
 196
 197   public:
 198
 199     /// @name Register information.
 200     /// The sum of numFPDestRegs() and numIntDestRegs() equals
 201     /// numDestRegs().  The former two functions are used to track
 202     /// physical register usage for machines with separate int & FP
 203     /// reg files.
 204     //@{
 205     /// Number of source registers.
 206     int8_t numSrcRegs()  const { return _numSrcRegs; }
 207     /// Number of destination registers.
 208     int8_t numDestRegs() const { return _numDestRegs; }
 209     /// Number of floating-point destination regs.
 210     int8_t numFPDestRegs()  const { return _numFPDestRegs; }
 211     /// Number of integer destination regs.
 212     int8_t numIntDestRegs() const { return _numIntDestRegs; }
 213     //@}
 214
 215     /// @name Flag accessors.
 216     /// These functions are used to access the values of the various
 217     /// instruction property flags.  See StaticInstBase::Flags for descriptions
 218     /// of the individual flags.
 219     //@{
 220
 221     bool isNop()          const { return flags[IsNop]; }
 222
 223     bool isMemRef()       const { return flags[IsMemRef]; }
 224     bool isLoad()         const { return flags[IsLoad]; }
 225     bool isStore()        const { return flags[IsStore]; }
 226     bool isStoreConditional()     const { return flags[IsStoreConditional]; }
 227     bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
 228     bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
 229     bool isCopy()         const { return flags[IsCopy];}
 230
 231     bool isInteger()      const { return flags[IsInteger]; }
 232     bool isFloating()     const { return flags[IsFloating]; }
 233
 234     bool isControl()      const { return flags[IsControl]; }
 235     bool isCall()         const { return flags[IsCall]; }
 236     bool isReturn()       const { return flags[IsReturn]; }
 237     bool isDirectCtrl()   const { return flags[IsDirectControl]; }
 238     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
 239     bool isCondCtrl()     const { return flags[IsCondControl]; }
 240     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 241     bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
 242
 243     bool isThreadSync()   const { return flags[IsThreadSync]; }
 244     bool isSerializing()  const { return flags[IsSerializing] ||
 245                                       flags[IsSerializeBefore] ||
 246                                       flags[IsSerializeAfter]; }
 247     bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
 248     bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
 249     bool isMemBarrier()   const { return flags[IsMemBarrier]; }
 250     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
 251     bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
 252     bool isQuiesce() const { return flags[IsQuiesce]; }
 253     bool isIprAccess() const { return flags[IsIprAccess]; }
 254     bool isUnverifiable() const { return flags[IsUnverifiable]; }
 255     bool isSyscall() const { return flags[IsSyscall]; }
 256     bool isMacroop() const { return flags[IsMacroop]; }
 257     bool isMicroop() const { return flags[IsMicroop]; }
 258     bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
 259     bool isLastMicroop() const { return flags[IsLastMicroop]; }
 260     bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
 261     //This flag doesn't do anything yet
 262     bool isMicroBranch() const { return flags[IsMicroBranch]; }
 263     //@}
 264
 265     void setLastMicroop() { flags[IsLastMicroop] = true; }
 266     void setDelayedCommit() { flags[IsDelayedCommit] = true; }
 267
 268     /// Operation class.  Used to select appropriate function unit in issue.
 269     OpClass opClass()     const { return _opClass; }
 270 };
 271
 272
 273 // forward declaration
 274 class StaticInstPtr;
 275
 276 /**
 277  * Generic yet ISA-dependent static instruction class.
 278  *
 279  * This class builds on StaticInstBase, defining fields and interfaces
 280  * that are generic across all ISAs but that differ in details
 281  * according to the specific ISA being used.
 282  */
 283 class StaticInst : public StaticInstBase
 284 {
 285   public:
 286
 287     /// Binary machine instruction type.
 288     typedef TheISA::MachInst MachInst;
 289     /// Binary extended machine instruction type.
 290     typedef TheISA::ExtMachInst ExtMachInst;
 291     /// Logical register index type.
 292     typedef TheISA::RegIndex RegIndex;
 293
 294     enum {
 295         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
 296         MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
 297     };
 298
 299
 300     /// Return logical index (architectural reg num) of i'th destination reg.
 301     /// Only the entries from 0 through numDestRegs()-1 are valid.
 302     RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
 303
 304     /// Return logical index (architectural reg num) of i'th source reg.
 305     /// Only the entries from 0 through numSrcRegs()-1 are valid.
 306     RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
 307
 308     /// Pointer to a statically allocated "null" instruction object.
 309     /// Used to give eaCompInst() and memAccInst() something to return
 310     /// when called on non-memory instructions.
 311     static StaticInstPtr nullStaticInstPtr;
 312
 313     /**
 314      * Memory references only: returns "fake" instruction representing
 315      * the effective address part of the memory operation.  Used to
 316      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 317      * just the EA computation.
 318      */
 319     virtual const
 320     StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
 321
 322     /**
 323      * Memory references only: returns "fake" instruction representing
 324      * the memory access part of the memory operation.  Used to
 325      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 326      * just the memory access (not the EA computation).
 327      */
 328     virtual const
 329     StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
 330
 331     /// The binary machine instruction.
 332     const ExtMachInst machInst;
 333
 334   protected:
 335
 336     /// See destRegIdx().
 337     RegIndex _destRegIdx[MaxInstDestRegs];
 338     /// See srcRegIdx().
 339     RegIndex _srcRegIdx[MaxInstSrcRegs];
 340
 341     /**
 342      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
 343      * methods.  Also useful to readily identify instructions from
 344      * within the debugger when #cachedDisassembly has not been
 345      * initialized.
 346      */
 347     const char *mnemonic;
 348
 349     /**
 350      * String representation of disassembly (lazily evaluated via
 351      * disassemble()).
 352      */
 353     mutable std::string *cachedDisassembly;
 354
 355     /**
 356      * Internal function to generate disassembly string.
 357      */
 358     virtual std::string
 359     generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 360
 361     /// Constructor.
 362     StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
 363         : StaticInstBase(__opClass),
 364           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
 365     { }
 366
 367   public:
 368     virtual ~StaticInst();
 369
 370 /**
 371  * The execute() signatures are auto-generated by scons based on the
 372  * set of CPU models we are compiling in today.
 373  */
 374 #include "cpu/static_inst_exec_sigs.hh"
 375
 376     virtual void advancePC(TheISA::PCState &pcState) const = 0;
 377
 378     /**
 379      * Return the microop that goes with a particular micropc. This should
 380      * only be defined/used in macroops which will contain microops
 381      */
 382     virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
 383
 384     /**
 385      * Return the target address for a PC-relative branch.
 386      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
 387      * should be true).
 388      */
 389     virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
 390
 391     /**
 392      * Return the target address for an indirect branch (jump).  The
 393      * register value is read from the supplied thread context, so
 394      * the result is valid only if the thread context is about to
 395      * execute the branch in question.  Invalid if not an indirect
 396      * branch (i.e. isIndirectCtrl() should be true).
 397      */
 398     virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
 399
 400     /**
 401      * Return true if the instruction is a control transfer, and if so,
 402      * return the target address as well.
 403      */
 404     bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
 405                          TheISA::PCState &tgt) const;
 406
 407     /**
 408      * Return string representation of disassembled instruction.
 409      * The default version of this function will call the internal
 410      * virtual generateDisassembly() function to get the string,
 411      * then cache it in #cachedDisassembly.  If the disassembly
 412      * should not be cached, this function should be overridden directly.
 413      */
 414     virtual const std::string &disassemble(Addr pc,
 415         const SymbolTable *symtab = 0) const;
 416
 417     /// Decoded instruction cache type.
 418     /// For now we're using a generic hash_map; this seems to work
 419     /// pretty well.
 420     typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
 421
 422     /// A cache of decoded instruction objects.
 423     static DecodeCache decodeCache;
 424
 425     /**
 426      * Dump some basic stats on the decode cache hash map.
 427      * Only gets called if DECODE_CACHE_HASH_STATS is defined.
 428      */
 429     static void dumpDecodeCacheStats();
 430
 431     /// Decode a machine instruction.
 432     /// @param mach_inst The binary instruction to decode.
 433     /// @retval A pointer to the corresponding StaticInst object.
 434     //This is defined as inlined below.
 435     static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
 436
 437     /// Return name of machine instruction
 438     std::string getName() { return mnemonic; }
 439
 440     /// Decoded instruction cache type, for address decoding.
 441     /// A generic hash_map is used.
 442     typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache;
 443
 444     /// A cache of decoded instruction objects from addresses.
 445     static AddrDecodeCache addrDecodeCache;
 446
 447     struct cacheElement
 448     {
 449         Addr page_addr;
 450         AddrDecodePage *decodePage;
 451
 452         cacheElement() : decodePage(NULL) { }
 453     };
 454
 455     /// An array of recently decoded instructions.
 456     // might not use an array if there is only two elements
 457     static struct cacheElement recentDecodes[2];
 458
 459     /// Updates the recently decoded instructions entries
 460     /// @param page_addr The page address recently used.
 461     /// @param decodePage Pointer to decoding page containing the decoded
 462     ///                   instruction.
 463     static inline void
 464     updateCache(Addr page_addr, AddrDecodePage *decodePage)
 465     {
 466         recentDecodes[1].page_addr = recentDecodes[0].page_addr;
 467         recentDecodes[1].decodePage = recentDecodes[0].decodePage;
 468         recentDecodes[0].page_addr = page_addr;
 469         recentDecodes[0].decodePage = decodePage;
 470     }
 471
 472     /// Searches the decoded instruction cache for instruction decoding.
 473     /// If it is not found, then we decode the instruction.
 474     /// Otherwise, we get the instruction from the cache and move it into
 475     /// the address-to-instruction decoding page.
 476     /// @param mach_inst The binary instruction to decode.
 477     /// @param addr The address that contained the binary instruction.
 478     /// @param decodePage Pointer to decoding page containing the instruction.
 479     /// @retval A pointer to the corresponding StaticInst object.
 480     //This is defined as inlined below.
 481     static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr,
 482                                      AddrDecodePage *decodePage);
 483 };
 484
 485 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
 486
 487 /// Reference-counted pointer to a StaticInst object.
 488 /// This type should be used instead of "StaticInst *" so that
 489 /// StaticInst objects can be properly reference-counted.
 490 class StaticInstPtr : public RefCountingPtr<StaticInst>
 491 {
 492   public:
 493     /// Constructor.
 494     StaticInstPtr()
 495         : RefCountingPtr<StaticInst>()
 496     {
 497     }
 498
 499     /// Conversion from "StaticInst *".
 500     StaticInstPtr(StaticInst *p)
 501         : RefCountingPtr<StaticInst>(p)
 502     {
 503     }
 504
 505     /// Copy constructor.
 506     StaticInstPtr(const StaticInstPtr &r)
 507         : RefCountingPtr<StaticInst>(r)
 508     {
 509     }
 510
 511     /// Construct directly from machine instruction.
 512     /// Calls StaticInst::decode().
 513     explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr)
 514         : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr))
 515     {
 516     }
 517
 518     /// Convert to pointer to StaticInstBase class.
 519     operator const StaticInstBasePtr()
 520     {
 521         return this->get();
 522     }
 523 };
 524
 525 /// A page of a list of decoded instructions from an address.
 526 class AddrDecodePage
 527 {
 528   typedef TheISA::ExtMachInst ExtMachInst;
 529   protected:
 530     StaticInstPtr instructions[TheISA::PageBytes];
 531     bool valid[TheISA::PageBytes];
 532     Addr lowerMask;
 533
 534   public:
 535     /// Constructor
 536     AddrDecodePage()
 537     {
 538         lowerMask = TheISA::PageBytes - 1;
 539         memset(valid, 0, TheISA::PageBytes);
 540     }
 541
 542     /// Checks if the instruction is already decoded and the machine
 543     /// instruction in the cache matches the current machine instruction
 544     /// related to the address
 545     /// @param mach_inst The binary instruction to check
 546     /// @param addr The address containing the instruction
 547     bool
 548     decoded(ExtMachInst mach_inst, Addr addr)
 549     {
 550         return (valid[addr & lowerMask] &&
 551                 (instructions[addr & lowerMask]->machInst == mach_inst));
 552     }
 553
 554     /// Returns the instruction object. decoded should be called first
 555     /// to check if the instruction is valid.
 556     /// @param addr The address of the instruction.
 557     /// @retval A pointer to the corresponding StaticInst object.
 558     StaticInstPtr
 559     getInst(Addr addr)
 560     {
 561         return instructions[addr & lowerMask];
 562     }
 563
 564     /// Inserts a pointer to a StaticInst object into the list of decoded
 565     /// instructions on the page.
 566     /// @param addr The address of the instruction.
 567     /// @param si A pointer to the corresponding StaticInst object.
 568     void
 569     insert(Addr addr, StaticInstPtr &si)
 570     {
 571         instructions[addr & lowerMask] = si;
 572         valid[addr & lowerMask] = true;
 573     }
 574 };
 575
 576
 577 inline StaticInstPtr
 578 StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
 579 {
 580 #ifdef DECODE_CACHE_HASH_STATS
 581     // Simple stats on decode hash_map.  Turns out the default
 582     // hash function is as good as anything I could come up with.
 583     const int dump_every_n = 10000000;
 584     static int decodes_til_dump = dump_every_n;
 585
 586     if (--decodes_til_dump == 0) {
 587         dumpDecodeCacheStats();
 588         decodes_til_dump = dump_every_n;
 589     }
 590 #endif
 591
 592     Addr page_addr = addr & ~(TheISA::PageBytes - 1);
 593
 594     // checks recently decoded addresses
 595     if (recentDecodes[0].decodePage &&
 596         page_addr == recentDecodes[0].page_addr) {
 597         if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
 598             return recentDecodes[0].decodePage->getInst(addr);
 599
 600         return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
 601     }
 602
 603     if (recentDecodes[1].decodePage &&
 604         page_addr == recentDecodes[1].page_addr) {
 605         if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
 606             return recentDecodes[1].decodePage->getInst(addr);
 607
 608         return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
 609     }
 610
 611     // searches the page containing the address to decode
 612     AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr);
 613     if (iter != addrDecodeCache.end()) {
 614         updateCache(page_addr, iter->second);
 615         if (iter->second->decoded(mach_inst, addr))
 616             return iter->second->getInst(addr);
 617
 618         return searchCache(mach_inst, addr, iter->second);
 619     }
 620
 621     // creates a new object for a page of decoded instructions
 622     AddrDecodePage *decodePage = new AddrDecodePage;
 623     addrDecodeCache[page_addr] = decodePage;
 624     updateCache(page_addr, decodePage);
 625     return searchCache(mach_inst, addr, decodePage);
 626 }
 627
 628 inline StaticInstPtr
 629 StaticInst::searchCache(ExtMachInst mach_inst, Addr addr,
 630                         AddrDecodePage *decodePage)
 631 {
 632     DecodeCache::iterator iter = decodeCache.find(mach_inst);
 633     if (iter != decodeCache.end()) {
 634         decodePage->insert(addr, iter->second);
 635         return iter->second;
 636     }
 637
 638     StaticInstPtr si = TheISA::decodeInst(mach_inst);
 639     decodePage->insert(addr, si);
 640     decodeCache[mach_inst] = si;
 641     return si;
 642 }
 643
 644 #endif // __CPU_STATIC_INST_HH__