src/cpu/testers/directedtest/InvalidateGenerator.cc

   1 /*
   2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
   3  * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include "cpu/testers/directedtest/InvalidateGenerator.hh"
  31
  32 #include "base/trace.hh"
  33 #include "cpu/testers/directedtest/DirectedGenerator.hh"
  34 #include "cpu/testers/directedtest/RubyDirectedTester.hh"
  35 #include "debug/DirectedTest.hh"
  36
  37 InvalidateGenerator::InvalidateGenerator(const Params *p)
  38     : DirectedGenerator(p)
  39 {
  40     //
  41     // First, issue loads to bring the block into S state
  42     //
  43     m_status = InvalidateGeneratorStatus_Load_Waiting;
  44     m_active_read_node = 0;
  45     m_active_inv_node = 0;
  46     m_address = 0x0;
  47     m_addr_increment_size = p->addr_increment_size;
  48 }
  49
  50 InvalidateGenerator::~InvalidateGenerator()
  51 {
  52 }
  53
  54 bool
  55 InvalidateGenerator::initiate()
  56 {
  57     RequestPort* port;
  58     Request::Flags flags;
  59     PacketPtr pkt;
  60     Packet::Command cmd;
  61
  62     // For simplicity, requests are assumed to be 1 byte-sized
  63     RequestPtr req = std::make_shared<Request>(m_address, 1, flags,
  64                                                requestorId);
  65
  66     //
  67     // Based on the current state, issue a load or a store
  68     //
  69     if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
  70         DPRINTF(DirectedTest, "initiating read\n");
  71         cmd = MemCmd::ReadReq;
  72         port = m_directed_tester->getCpuPort(m_active_read_node);
  73         pkt = new Packet(req, cmd);
  74     } else if (m_status == InvalidateGeneratorStatus_Inv_Waiting) {
  75         DPRINTF(DirectedTest, "initiating invalidating write\n");
  76         cmd = MemCmd::WriteReq;
  77         port = m_directed_tester->getCpuPort(m_active_inv_node);
  78         pkt = new Packet(req, cmd);
  79     } else {
  80         panic("initiate was unexpectedly called\n");
  81     }
  82     pkt->allocate();
  83
  84     if (port->sendTimingReq(pkt)) {
  85         DPRINTF(DirectedTest, "initiating request - successful\n");
  86         if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
  87             m_status = InvalidateGeneratorStatus_Load_Pending;
  88         } else {
  89             m_status = InvalidateGeneratorStatus_Inv_Pending;
  90         }
  91         return true;
  92     } else {
  93         // If the packet did not issue, must delete
  94         // Note: No need to delete the data, the packet destructor
  95         // will delete it
  96         delete pkt;
  97
  98         DPRINTF(DirectedTest, "failed to issue request - sequencer not ready\n");
  99         return false;
 100     }
 101 }
 102
 103 void
 104 InvalidateGenerator::performCallback(uint32_t proc, Addr address)
 105 {
 106     assert(m_address == address);
 107
 108     if (m_status == InvalidateGeneratorStatus_Load_Pending) {
 109         assert(m_active_read_node == proc);
 110         m_active_read_node++;
 111         //
 112         // Once all cpus have the block in S state, issue the invalidate
 113         //
 114         if (m_active_read_node == m_num_cpus) {
 115             m_status = InvalidateGeneratorStatus_Inv_Waiting;
 116             m_active_read_node = 0;
 117         } else {
 118             m_status = InvalidateGeneratorStatus_Load_Waiting;
 119         }
 120     } else if (m_status == InvalidateGeneratorStatus_Inv_Pending) {
 121         assert(m_active_inv_node == proc);
 122         m_active_inv_node++;
 123         if (m_active_inv_node == m_num_cpus) {
 124             m_address += m_addr_increment_size;
 125             m_active_inv_node = 0;
 126         }
 127         //
 128         // Invalidate completed, send that info to the tester and restart
 129         // the cycle
 130         //
 131         m_directed_tester->incrementCycleCompletions();
 132         m_status = InvalidateGeneratorStatus_Load_Waiting;
 133     }
 134
 135 }
 136
 137 InvalidateGenerator *
 138 InvalidateGeneratorParams::create()
 139 {
 140     return new InvalidateGenerator(this);
 141 }