sim: Move the draining interface into a separate base class
[gem5.git] / src / cpu / testers / directedtest / RubyDirectedTester.py
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27 # Authors: Brad Beckmann
28
29 from m5.SimObject import SimObject
30 from MemObject import MemObject
31 from m5.params import *
32 from m5.proxy import *
33
34 class DirectedGenerator(SimObject):
35 type = 'DirectedGenerator'
36 abstract = True
37 cxx_header = "cpu/testers/directedtest/DirectedGenerator.hh"
38 num_cpus = Param.Int("num of cpus")
39 system = Param.System(Parent.any, "System we belong to")
40
41 class SeriesRequestGenerator(DirectedGenerator):
42 type = 'SeriesRequestGenerator'
43 cxx_header = "cpu/testers/directedtest/SeriesRequestGenerator.hh"
44 addr_increment_size = Param.Int(64, "address increment size")
45 issue_writes = Param.Bool(True, "issue writes if true, otherwise reads")
46
47 class InvalidateGenerator(DirectedGenerator):
48 type = 'InvalidateGenerator'
49 cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh"
50 addr_increment_size = Param.Int(64, "address increment size")
51
52 class RubyDirectedTester(MemObject):
53 type = 'RubyDirectedTester'
54 cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh"
55 cpuPort = VectorMasterPort("the cpu ports")
56 requests_to_complete = Param.Int("checks to complete")
57 generator = Param.DirectedGenerator("the request generator")