2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
32 // FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
39 #include "base/misc.hh"
40 #include "base/statistics.hh"
41 #include "cpu/testers/memtest/memtest.hh"
42 #include "debug/MemTest.hh"
43 #include "mem/mem_object.hh"
44 #include "mem/packet.hh"
45 #include "mem/port.hh"
46 #include "mem/request.hh"
47 #include "sim/sim_events.hh"
48 #include "sim/stats.hh"
49 #include "sim/system.hh"
53 int TESTER_ALLOCATOR
=0;
56 MemTest::CpuPort::recvTiming(PacketPtr pkt
)
58 assert(pkt
->isResponse());
59 memtest
->completeRequest(pkt
);
64 MemTest::CpuPort::recvRetry()
70 MemTest::sendPkt(PacketPtr pkt
) {
72 cachePort
.sendAtomic(pkt
);
75 else if (!cachePort
.sendTiming(pkt
)) {
76 DPRINTF(MemTest
, "accessRetry setting to true\n");
79 // dma requests should never be retried
82 panic("Nacked DMA requests are not supported\n");
88 dmaOutstanding
= true;
94 MemTest::MemTest(const Params
*p
)
97 cachePort("test", this),
98 funcPort("functional", this),
101 // mainMem(main_mem),
102 // checkMem(check_mem),
103 size(p
->memory_size
),
104 percentReads(p
->percent_reads
),
105 percentFunctional(p
->percent_functional
),
106 percentUncacheable(p
->percent_uncacheable
),
107 issueDmas(p
->issue_dmas
),
108 masterId(p
->sys
->getMasterId(name())),
109 progressInterval(p
->progress_interval
),
110 nextProgressMessage(p
->progress_interval
),
111 percentSourceUnaligned(p
->percent_source_unaligned
),
112 percentDestUnaligned(p
->percent_dest_unaligned
),
113 maxLoads(p
->max_loads
),
115 suppress_func_warnings(p
->suppress_func_warnings
)
117 id
= TESTER_ALLOCATOR
++;
119 // Needs to be masked off once we know the block size.
120 traceBlockAddr
= p
->trace_addr
;
121 baseAddr1
= 0x100000;
122 baseAddr2
= 0x400000;
123 uncacheAddr
= 0x800000;
126 noResponseCycles
= 0;
129 schedule(tickEvent
, 0);
132 dmaOutstanding
= false;
136 MemTest::getMasterPort(const std::string
&if_name
, int idx
)
138 if (if_name
== "functional")
140 else if (if_name
== "test")
143 return MemObject::getMasterPort(if_name
, idx
);
149 // By the time init() is called, the ports should be hooked up.
150 blockSize
= cachePort
.peerBlockSize();
151 blockAddrMask
= blockSize
- 1;
152 traceBlockAddr
= blockAddr(traceBlockAddr
);
154 // initial memory contents for both physical memory and functional
155 // memory should be 0; no need to initialize them.
160 MemTest::completeRequest(PacketPtr pkt
)
162 Request
*req
= pkt
->req
;
165 dmaOutstanding
= false;
168 DPRINTF(MemTest
, "completing %s at address %x (blk %x) %s\n",
169 pkt
->isWrite() ? "write" : "read",
170 req
->getPaddr(), blockAddr(req
->getPaddr()),
171 pkt
->isError() ? "error" : "success");
173 MemTestSenderState
*state
=
174 dynamic_cast<MemTestSenderState
*>(pkt
->senderState
);
176 uint8_t *data
= state
->data
;
177 uint8_t *pkt_data
= pkt
->getPtr
<uint8_t>();
179 //Remove the address from the list of outstanding
180 std::set
<unsigned>::iterator removeAddr
=
181 outstandingAddrs
.find(req
->getPaddr());
182 assert(removeAddr
!= outstandingAddrs
.end());
183 outstandingAddrs
.erase(removeAddr
);
185 if (pkt
->isError()) {
186 if (!suppress_func_warnings
) {
187 warn("Functional Access failed for %x at %x\n",
188 pkt
->isWrite() ? "write" : "read", req
->getPaddr());
192 if (memcmp(pkt_data
, data
, pkt
->getSize()) != 0) {
193 panic("%s: read of %x (blk %x) @ cycle %d "
194 "returns %x, expected %x\n", name(),
195 req
->getPaddr(), blockAddr(req
->getPaddr()), curTick(),
202 if (numReads
== (uint64_t)nextProgressMessage
) {
203 ccprintf(cerr
, "%s: completed %d read, %d write accesses @%d\n",
204 name(), numReads
, numWrites
, curTick());
205 nextProgressMessage
+= progressInterval
;
208 if (maxLoads
!= 0 && numReads
>= maxLoads
)
209 exitSimLoop("maximum number of loads reached");
211 assert(pkt
->isWrite());
212 funcProxy
.writeBlob(req
->getPaddr(), pkt_data
, req
->getSize());
218 noResponseCycles
= 0;
228 using namespace Stats
;
231 .name(name() + ".num_reads")
232 .desc("number of read accesses completed")
236 .name(name() + ".num_writes")
237 .desc("number of write accesses completed")
241 .name(name() + ".num_copies")
242 .desc("number of copy accesses completed")
249 if (!tickEvent
.scheduled())
250 schedule(tickEvent
, curTick() + ticks(1));
252 if (++noResponseCycles
>= 500000) {
254 cerr
<< "DMA tester ";
256 cerr
<< name() << ": deadlocked at cycle " << curTick() << endl
;
260 if (accessRetry
|| (issueDmas
&& dmaOutstanding
)) {
261 DPRINTF(MemTest
, "MemTester waiting on accessRetry or DMA response\n");
266 unsigned cmd
= random() % 100;
267 unsigned offset
= random() % size
;
268 unsigned base
= random() % 2;
269 uint64_t data
= random();
270 unsigned access_size
= random() % 4;
271 bool uncacheable
= (random() % 100) < percentUncacheable
;
273 unsigned dma_access_size
= random() % 4;
275 //If we aren't doing copies, use id as offset, and do a false sharing
277 //We can eliminate the lower bits of the offset, and then use the id
278 //to offset within the blks
279 offset
= blockAddr(offset
);
284 Request
*req
= new Request();
285 Request::Flags flags
;
289 flags
.set(Request::UNCACHEABLE
);
290 paddr
= uncacheAddr
+ offset
;
292 paddr
= ((base
) ? baseAddr1
: baseAddr2
) + offset
;
294 bool do_functional
= (random() % 100 < percentFunctional
) && !uncacheable
;
297 paddr
&= ~((1 << dma_access_size
) - 1);
298 req
->setPhys(paddr
, 1 << dma_access_size
, flags
, masterId
);
299 req
->setThreadContext(id
,0);
301 paddr
&= ~((1 << access_size
) - 1);
302 req
->setPhys(paddr
, 1 << access_size
, flags
, masterId
);
303 req
->setThreadContext(id
,0);
305 assert(req
->getSize() == 1);
307 uint8_t *result
= new uint8_t[8];
309 if (cmd
< percentReads
) {
312 // For now we only allow one outstanding request per address
313 // per tester This means we assume CPU does write forwarding
314 // to reads that alias something in the cpu store buffer.
315 if (outstandingAddrs
.find(paddr
) != outstandingAddrs
.end()) {
321 outstandingAddrs
.insert(paddr
);
323 // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
324 funcProxy
.readBlob(req
->getPaddr(), result
, req
->getSize());
327 "id %d initiating %sread at addr %x (blk %x) expecting %x\n",
328 id
, do_functional
? "functional " : "", req
->getPaddr(),
329 blockAddr(req
->getPaddr()), *result
);
331 PacketPtr pkt
= new Packet(req
, MemCmd::ReadReq
);
332 pkt
->dataDynamicArray(new uint8_t[req
->getSize()]);
333 MemTestSenderState
*state
= new MemTestSenderState(result
);
334 pkt
->senderState
= state
;
337 assert(pkt
->needsResponse());
338 pkt
->setSuppressFuncError();
339 cachePort
.sendFunctional(pkt
);
340 completeRequest(pkt
);
347 // For now we only allow one outstanding request per addreess
348 // per tester. This means we assume CPU does write forwarding
349 // to reads that alias something in the cpu store buffer.
350 if (outstandingAddrs
.find(paddr
) != outstandingAddrs
.end()) {
356 outstandingAddrs
.insert(paddr
);
358 DPRINTF(MemTest
, "initiating %swrite at addr %x (blk %x) value %x\n",
359 do_functional
? "functional " : "", req
->getPaddr(),
360 blockAddr(req
->getPaddr()), data
& 0xff);
362 PacketPtr pkt
= new Packet(req
, MemCmd::WriteReq
);
363 uint8_t *pkt_data
= new uint8_t[req
->getSize()];
364 pkt
->dataDynamicArray(pkt_data
);
365 memcpy(pkt_data
, &data
, req
->getSize());
366 MemTestSenderState
*state
= new MemTestSenderState(result
);
367 pkt
->senderState
= state
;
370 pkt
->setSuppressFuncError();
371 cachePort
.sendFunctional(pkt
);
372 completeRequest(pkt
);
382 if (cachePort
.sendTiming(retryPkt
)) {
383 DPRINTF(MemTest
, "accessRetry setting to false\n");
391 MemTest::printAddr(Addr a
)
393 cachePort
.printAddr(a
);
398 MemTestParams::create()
400 return new MemTest(this);