d75bcb845b3238f08591e4edbf6302f1d4b55f5d
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
32 // FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
39 #include "base/misc.hh"
40 #include "base/statistics.hh"
41 #include "cpu/testers/memtest/memtest.hh"
42 #include "debug/MemTest.hh"
43 #include "mem/mem_object.hh"
44 #include "mem/packet.hh"
45 #include "mem/port.hh"
46 #include "mem/request.hh"
47 #include "sim/sim_events.hh"
48 #include "sim/stats.hh"
52 int TESTER_ALLOCATOR
=0;
55 MemTest::CpuPort::recvTiming(PacketPtr pkt
)
57 if (pkt
->isResponse()) {
58 memtest
->completeRequest(pkt
);
60 // must be snoop upcall
61 assert(pkt
->isRequest());
62 assert(pkt
->getDest() == Packet::Broadcast
);
68 MemTest::CpuPort::recvAtomic(PacketPtr pkt
)
70 // must be snoop upcall
71 assert(pkt
->isRequest());
72 assert(pkt
->getDest() == Packet::Broadcast
);
77 MemTest::CpuPort::recvFunctional(PacketPtr pkt
)
79 //Do nothing if we see one come through
80 // if (curTick() != 0)//Supress warning durring initialization
81 // warn("Functional Writes not implemented in MemTester\n");
82 //Need to find any response values that intersect and update
87 MemTest::CpuPort::recvStatusChange(Status status
)
89 if (status
== RangeChange
) {
90 if (!snoopRangeSent
) {
91 snoopRangeSent
= true;
92 sendStatusChange(Port::RangeChange
);
97 panic("MemTest doesn't expect recvStatusChange callback!");
101 MemTest::CpuPort::recvRetry()
107 MemTest::sendPkt(PacketPtr pkt
) {
109 cachePort
.sendAtomic(pkt
);
110 completeRequest(pkt
);
112 else if (!cachePort
.sendTiming(pkt
)) {
113 DPRINTF(MemTest
, "accessRetry setting to true\n");
116 // dma requests should never be retried
119 panic("Nacked DMA requests are not supported\n");
125 dmaOutstanding
= true;
131 MemTest::MemTest(const Params
*p
)
134 cachePort("test", this),
135 funcPort("functional", this),
137 // mainMem(main_mem),
138 // checkMem(check_mem),
139 size(p
->memory_size
),
140 percentReads(p
->percent_reads
),
141 percentFunctional(p
->percent_functional
),
142 percentUncacheable(p
->percent_uncacheable
),
143 issueDmas(p
->issue_dmas
),
144 progressInterval(p
->progress_interval
),
145 nextProgressMessage(p
->progress_interval
),
146 percentSourceUnaligned(p
->percent_source_unaligned
),
147 percentDestUnaligned(p
->percent_dest_unaligned
),
148 maxLoads(p
->max_loads
),
151 cachePort
.snoopRangeSent
= false;
152 funcPort
.snoopRangeSent
= true;
154 id
= TESTER_ALLOCATOR
++;
156 // Needs to be masked off once we know the block size.
157 traceBlockAddr
= p
->trace_addr
;
158 baseAddr1
= 0x100000;
159 baseAddr2
= 0x400000;
160 uncacheAddr
= 0x800000;
163 noResponseCycles
= 0;
165 schedule(tickEvent
, 0);
168 dmaOutstanding
= false;
172 MemTest::getPort(const std::string
&if_name
, int idx
)
174 if (if_name
== "functional")
176 else if (if_name
== "test")
179 panic("No Such Port\n");
185 // By the time init() is called, the ports should be hooked up.
186 blockSize
= cachePort
.peerBlockSize();
187 blockAddrMask
= blockSize
- 1;
188 traceBlockAddr
= blockAddr(traceBlockAddr
);
190 // initial memory contents for both physical memory and functional
191 // memory should be 0; no need to initialize them.
196 MemTest::completeRequest(PacketPtr pkt
)
198 Request
*req
= pkt
->req
;
201 dmaOutstanding
= false;
204 DPRINTF(MemTest
, "completing %s at address %x (blk %x)\n",
205 pkt
->isWrite() ? "write" : "read",
206 req
->getPaddr(), blockAddr(req
->getPaddr()));
208 MemTestSenderState
*state
=
209 dynamic_cast<MemTestSenderState
*>(pkt
->senderState
);
211 uint8_t *data
= state
->data
;
212 uint8_t *pkt_data
= pkt
->getPtr
<uint8_t>();
214 //Remove the address from the list of outstanding
215 std::set
<unsigned>::iterator removeAddr
=
216 outstandingAddrs
.find(req
->getPaddr());
217 assert(removeAddr
!= outstandingAddrs
.end());
218 outstandingAddrs
.erase(removeAddr
);
221 if (memcmp(pkt_data
, data
, pkt
->getSize()) != 0) {
222 panic("%s: read of %x (blk %x) @ cycle %d "
223 "returns %x, expected %x\n", name(),
224 req
->getPaddr(), blockAddr(req
->getPaddr()), curTick(),
231 if (numReads
== (uint64_t)nextProgressMessage
) {
232 ccprintf(cerr
, "%s: completed %d read accesses @%d\n",
233 name(), numReads
, curTick());
234 nextProgressMessage
+= progressInterval
;
237 if (maxLoads
!= 0 && numReads
>= maxLoads
)
238 exitSimLoop("maximum number of loads reached");
240 assert(pkt
->isWrite());
244 noResponseCycles
= 0;
254 using namespace Stats
;
257 .name(name() + ".num_reads")
258 .desc("number of read accesses completed")
262 .name(name() + ".num_writes")
263 .desc("number of write accesses completed")
267 .name(name() + ".num_copies")
268 .desc("number of copy accesses completed")
275 if (!tickEvent
.scheduled())
276 schedule(tickEvent
, curTick() + ticks(1));
278 if (++noResponseCycles
>= 500000) {
280 cerr
<< "DMA tester ";
282 cerr
<< name() << ": deadlocked at cycle " << curTick() << endl
;
286 if (accessRetry
|| (issueDmas
&& dmaOutstanding
)) {
287 DPRINTF(MemTest
, "MemTester waiting on accessRetry or DMA response\n");
292 unsigned cmd
= random() % 100;
293 unsigned offset
= random() % size
;
294 unsigned base
= random() % 2;
295 uint64_t data
= random();
296 unsigned access_size
= random() % 4;
297 bool uncacheable
= (random() % 100) < percentUncacheable
;
299 unsigned dma_access_size
= random() % 4;
301 //If we aren't doing copies, use id as offset, and do a false sharing
303 //We can eliminate the lower bits of the offset, and then use the id
304 //to offset within the blks
305 offset
= blockAddr(offset
);
310 Request
*req
= new Request();
311 Request::Flags flags
;
315 flags
.set(Request::UNCACHEABLE
);
316 paddr
= uncacheAddr
+ offset
;
318 paddr
= ((base
) ? baseAddr1
: baseAddr2
) + offset
;
320 bool do_functional
= (random() % 100 < percentFunctional
) && !uncacheable
;
323 paddr
&= ~((1 << dma_access_size
) - 1);
324 req
->setPhys(paddr
, 1 << dma_access_size
, flags
);
325 req
->setThreadContext(id
,0);
327 paddr
&= ~((1 << access_size
) - 1);
328 req
->setPhys(paddr
, 1 << access_size
, flags
);
329 req
->setThreadContext(id
,0);
331 assert(req
->getSize() == 1);
333 uint8_t *result
= new uint8_t[8];
335 if (cmd
< percentReads
) {
338 // For now we only allow one outstanding request per address
339 // per tester This means we assume CPU does write forwarding
340 // to reads that alias something in the cpu store buffer.
341 if (outstandingAddrs
.find(paddr
) != outstandingAddrs
.end()) {
347 outstandingAddrs
.insert(paddr
);
349 // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
350 funcPort
.readBlob(req
->getPaddr(), result
, req
->getSize());
353 "id %d initiating %sread at addr %x (blk %x) expecting %x\n",
354 id
, do_functional
? "functional " : "", req
->getPaddr(),
355 blockAddr(req
->getPaddr()), *result
);
357 PacketPtr pkt
= new Packet(req
, MemCmd::ReadReq
, Packet::Broadcast
);
359 pkt
->dataDynamicArray(new uint8_t[req
->getSize()]);
360 MemTestSenderState
*state
= new MemTestSenderState(result
);
361 pkt
->senderState
= state
;
364 cachePort
.sendFunctional(pkt
);
365 completeRequest(pkt
);
372 // For now we only allow one outstanding request per addreess
373 // per tester. This means we assume CPU does write forwarding
374 // to reads that alias something in the cpu store buffer.
375 if (outstandingAddrs
.find(paddr
) != outstandingAddrs
.end()) {
381 outstandingAddrs
.insert(paddr
);
383 DPRINTF(MemTest
, "initiating %swrite at addr %x (blk %x) value %x\n",
384 do_functional
? "functional " : "", req
->getPaddr(),
385 blockAddr(req
->getPaddr()), data
& 0xff);
387 PacketPtr pkt
= new Packet(req
, MemCmd::WriteReq
, Packet::Broadcast
);
389 uint8_t *pkt_data
= new uint8_t[req
->getSize()];
390 pkt
->dataDynamicArray(pkt_data
);
391 memcpy(pkt_data
, &data
, req
->getSize());
392 MemTestSenderState
*state
= new MemTestSenderState(result
);
393 pkt
->senderState
= state
;
395 funcPort
.writeBlob(req
->getPaddr(), pkt_data
, req
->getSize());
398 cachePort
.sendFunctional(pkt
);
399 completeRequest(pkt
);
409 if (cachePort
.sendTiming(retryPkt
)) {
410 DPRINTF(MemTest
, "accessRetry setting to false\n");
418 MemTest::printAddr(Addr a
)
420 cachePort
.printAddr(a
);
425 MemTestParams::create()
427 return new MemTest(this);