src/cpu/testers/memtest/memtest.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Steve Reinhardt
  30  */
  31
  32 // FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
  33
  34 #include <iomanip>
  35 #include <set>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "base/misc.hh"
  40 #include "base/statistics.hh"
  41 #include "cpu/testers/memtest/memtest.hh"
  42 #include "mem/mem_object.hh"
  43 #include "mem/port.hh"
  44 #include "mem/packet.hh"
  45 #include "mem/request.hh"
  46 #include "sim/sim_events.hh"
  47 #include "sim/stats.hh"
  48
  49 using namespace std;
  50
  51 int TESTER_ALLOCATOR=0;
  52
  53 bool
  54 MemTest::CpuPort::recvTiming(PacketPtr pkt)
  55 {
  56     if (pkt->isResponse()) {
  57         memtest->completeRequest(pkt);
  58     } else {
  59         // must be snoop upcall
  60         assert(pkt->isRequest());
  61         assert(pkt->getDest() == Packet::Broadcast);
  62     }
  63     return true;
  64 }
  65
  66 Tick
  67 MemTest::CpuPort::recvAtomic(PacketPtr pkt)
  68 {
  69     // must be snoop upcall
  70     assert(pkt->isRequest());
  71     assert(pkt->getDest() == Packet::Broadcast);
  72     return curTick;
  73 }
  74
  75 void
  76 MemTest::CpuPort::recvFunctional(PacketPtr pkt)
  77 {
  78     //Do nothing if we see one come through
  79 //    if (curTick != 0)//Supress warning durring initialization
  80 //        warn("Functional Writes not implemented in MemTester\n");
  81     //Need to find any response values that intersect and update
  82     return;
  83 }
  84
  85 void
  86 MemTest::CpuPort::recvStatusChange(Status status)
  87 {
  88     if (status == RangeChange) {
  89         if (!snoopRangeSent) {
  90             snoopRangeSent = true;
  91             sendStatusChange(Port::RangeChange);
  92         }
  93         return;
  94     }
  95
  96     panic("MemTest doesn't expect recvStatusChange callback!");
  97 }
  98
  99 void
 100 MemTest::CpuPort::recvRetry()
 101 {
 102     memtest->doRetry();
 103 }
 104
 105 void
 106 MemTest::sendPkt(PacketPtr pkt) {
 107     if (atomic) {
 108         cachePort.sendAtomic(pkt);
 109         completeRequest(pkt);
 110     }
 111     else if (!cachePort.sendTiming(pkt)) {
 112         DPRINTF(MemTest, "accessRetry setting to true\n");
 113
 114         //
 115         // dma requests should never be retried
 116         //
 117         if (issueDmas) {
 118             panic("Nacked DMA requests are not supported\n");
 119         }
 120         accessRetry = true;
 121         retryPkt = pkt;
 122     } else {
 123         if (issueDmas) {
 124             dmaOutstanding = true;
 125         }
 126     }
 127
 128 }
 129
 130 MemTest::MemTest(const Params *p)
 131     : MemObject(p),
 132       tickEvent(this),
 133       cachePort("test", this),
 134       funcPort("functional", this),
 135       retryPkt(NULL),
 136 //      mainMem(main_mem),
 137 //      checkMem(check_mem),
 138       size(p->memory_size),
 139       percentReads(p->percent_reads),
 140       percentFunctional(p->percent_functional),
 141       percentUncacheable(p->percent_uncacheable),
 142       issueDmas(p->issue_dmas),
 143       progressInterval(p->progress_interval),
 144       nextProgressMessage(p->progress_interval),
 145       percentSourceUnaligned(p->percent_source_unaligned),
 146       percentDestUnaligned(p->percent_dest_unaligned),
 147       maxLoads(p->max_loads),
 148       atomic(p->atomic)
 149 {
 150
 151     vector<string> cmd;
 152     cmd.push_back("/bin/ls");
 153     vector<string> null_vec;
 154     //  thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
 155     curTick = 0;
 156
 157     cachePort.snoopRangeSent = false;
 158     funcPort.snoopRangeSent = true;
 159
 160     id = TESTER_ALLOCATOR++;
 161
 162     // Needs to be masked off once we know the block size.
 163     traceBlockAddr = p->trace_addr;
 164     baseAddr1 = 0x100000;
 165     baseAddr2 = 0x400000;
 166     uncacheAddr = 0x800000;
 167
 168     // set up counters
 169     noResponseCycles = 0;
 170     numReads = 0;
 171     schedule(tickEvent, 0);
 172
 173     accessRetry = false;
 174     dmaOutstanding = false;
 175 }
 176
 177 Port *
 178 MemTest::getPort(const std::string &if_name, int idx)
 179 {
 180     if (if_name == "functional")
 181         return &funcPort;
 182     else if (if_name == "test")
 183         return &cachePort;
 184     else
 185         panic("No Such Port\n");
 186 }
 187
 188 void
 189 MemTest::init()
 190 {
 191     // By the time init() is called, the ports should be hooked up.
 192     blockSize = cachePort.peerBlockSize();
 193     blockAddrMask = blockSize - 1;
 194     traceBlockAddr = blockAddr(traceBlockAddr);
 195
 196     // initial memory contents for both physical memory and functional
 197     // memory should be 0; no need to initialize them.
 198 }
 199
 200
 201 void
 202 MemTest::completeRequest(PacketPtr pkt)
 203 {
 204     Request *req = pkt->req;
 205
 206     if (issueDmas) {
 207         dmaOutstanding = false;
 208     }
 209
 210     DPRINTF(MemTest, "completing %s at address %x (blk %x)\n",
 211             pkt->isWrite() ? "write" : "read",
 212             req->getPaddr(), blockAddr(req->getPaddr()));
 213
 214     MemTestSenderState *state =
 215         dynamic_cast<MemTestSenderState *>(pkt->senderState);
 216
 217     uint8_t *data = state->data;
 218     uint8_t *pkt_data = pkt->getPtr<uint8_t>();
 219
 220     //Remove the address from the list of outstanding
 221     std::set<unsigned>::iterator removeAddr =
 222         outstandingAddrs.find(req->getPaddr());
 223     assert(removeAddr != outstandingAddrs.end());
 224     outstandingAddrs.erase(removeAddr);
 225
 226     assert(pkt->isResponse());
 227
 228     if (pkt->isRead()) {
 229         if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
 230             panic("%s: read of %x (blk %x) @ cycle %d "
 231                   "returns %x, expected %x\n", name(),
 232                   req->getPaddr(), blockAddr(req->getPaddr()), curTick,
 233                   *pkt_data, *data);
 234         }
 235
 236         numReads++;
 237         numReadsStat++;
 238
 239         if (numReads == (uint64_t)nextProgressMessage) {
 240             ccprintf(cerr, "%s: completed %d read accesses @%d\n",
 241                      name(), numReads, curTick);
 242             nextProgressMessage += progressInterval;
 243         }
 244
 245         if (maxLoads != 0 && numReads >= maxLoads)
 246             exitSimLoop("maximum number of loads reached");
 247     } else {
 248         assert(pkt->isWrite());
 249         numWritesStat++;
 250     }
 251
 252     noResponseCycles = 0;
 253     delete state;
 254     delete [] data;
 255     delete pkt->req;
 256     delete pkt;
 257 }
 258
 259 void
 260 MemTest::regStats()
 261 {
 262     using namespace Stats;
 263
 264     numReadsStat
 265         .name(name() + ".num_reads")
 266         .desc("number of read accesses completed")
 267         ;
 268
 269     numWritesStat
 270         .name(name() + ".num_writes")
 271         .desc("number of write accesses completed")
 272         ;
 273
 274     numCopiesStat
 275         .name(name() + ".num_copies")
 276         .desc("number of copy accesses completed")
 277         ;
 278 }
 279
 280 void
 281 MemTest::tick()
 282 {
 283     if (!tickEvent.scheduled())
 284         schedule(tickEvent, curTick + ticks(1));
 285
 286     if (++noResponseCycles >= 500000) {
 287         if (issueDmas) {
 288             cerr << "DMA tester ";
 289         }
 290         cerr << name() << ": deadlocked at cycle " << curTick << endl;
 291         fatal("");
 292     }
 293
 294     if (accessRetry || (issueDmas && dmaOutstanding)) {
 295         DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
 296         return;
 297     }
 298
 299     //make new request
 300     unsigned cmd = random() % 100;
 301     unsigned offset = random() % size;
 302     unsigned base = random() % 2;
 303     uint64_t data = random();
 304     unsigned access_size = random() % 4;
 305     bool uncacheable = (random() % 100) < percentUncacheable;
 306
 307     unsigned dma_access_size = random() % 4;
 308
 309     //If we aren't doing copies, use id as offset, and do a false sharing
 310     //mem tester
 311     //We can eliminate the lower bits of the offset, and then use the id
 312     //to offset within the blks
 313     offset = blockAddr(offset);
 314     offset += id;
 315     access_size = 0;
 316     dma_access_size = 0;
 317
 318     Request *req = new Request();
 319     Request::Flags flags;
 320     Addr paddr;
 321
 322     if (uncacheable) {
 323         flags.set(Request::UNCACHEABLE);
 324         paddr = uncacheAddr + offset;
 325     } else  {
 326         paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
 327     }
 328     bool probe = (random() % 100 < percentFunctional) && !uncacheable;
 329
 330     if (issueDmas) {
 331         paddr &= ~((1 << dma_access_size) - 1);
 332         req->setPhys(paddr, 1 << dma_access_size, flags);
 333         req->setThreadContext(id,0);
 334     } else {
 335         paddr &= ~((1 << access_size) - 1);
 336         req->setPhys(paddr, 1 << access_size, flags);
 337         req->setThreadContext(id,0);
 338     }
 339     assert(req->getSize() == 1);
 340
 341     uint8_t *result = new uint8_t[8];
 342
 343     if (cmd < percentReads) {
 344         // read
 345
 346         // For now we only allow one outstanding request per address
 347         // per tester This means we assume CPU does write forwarding
 348         // to reads that alias something in the cpu store buffer.
 349         if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
 350             delete [] result;
 351             delete req;
 352             return;
 353         }
 354
 355         outstandingAddrs.insert(paddr);
 356
 357         // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
 358         funcPort.readBlob(req->getPaddr(), result, req->getSize());
 359
 360         DPRINTF(MemTest,
 361                 "id %d initiating read at address %x (blk %x) expecting %x\n",
 362                 id, req->getPaddr(), blockAddr(req->getPaddr()), *result);
 363
 364         PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
 365         pkt->setSrc(0);
 366         pkt->dataDynamicArray(new uint8_t[req->getSize()]);
 367         MemTestSenderState *state = new MemTestSenderState(result);
 368         pkt->senderState = state;
 369
 370         if (probe) {
 371             cachePort.sendFunctional(pkt);
 372             completeRequest(pkt);
 373         } else {
 374             sendPkt(pkt);
 375         }
 376     } else {
 377         // write
 378
 379         // For now we only allow one outstanding request per addreess
 380         // per tester.  This means we assume CPU does write forwarding
 381         // to reads that alias something in the cpu store buffer.
 382         if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
 383             delete [] result;
 384             delete req;
 385             return;
 386         }
 387
 388         outstandingAddrs.insert(paddr);
 389
 390         DPRINTF(MemTest, "initiating write at address %x (blk %x) value %x\n",
 391                 req->getPaddr(), blockAddr(req->getPaddr()), data & 0xff);
 392
 393         PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
 394         pkt->setSrc(0);
 395         uint8_t *pkt_data = new uint8_t[req->getSize()];
 396         pkt->dataDynamicArray(pkt_data);
 397         memcpy(pkt_data, &data, req->getSize());
 398         MemTestSenderState *state = new MemTestSenderState(result);
 399         pkt->senderState = state;
 400
 401         funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize());
 402
 403         if (probe) {
 404             cachePort.sendFunctional(pkt);
 405             completeRequest(pkt);
 406         } else {
 407             sendPkt(pkt);
 408         }
 409     }
 410 }
 411
 412 void
 413 MemTest::doRetry()
 414 {
 415     if (cachePort.sendTiming(retryPkt)) {
 416         DPRINTF(MemTest, "accessRetry setting to false\n");
 417         accessRetry = false;
 418         retryPkt = NULL;
 419     }
 420 }
 421
 422
 423 void
 424 MemTest::printAddr(Addr a)
 425 {
 426     cachePort.printAddr(a);
 427 }
 428
 429
 430 MemTest *
 431 MemTestParams::create()
 432 {
 433     return new MemTest(this);
 434 }