2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
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9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
32 // FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
39 #include "base/misc.hh"
40 #include "base/statistics.hh"
41 #include "cpu/testers/memtest/memtest.hh"
42 #include "mem/mem_object.hh"
43 #include "mem/port.hh"
44 #include "mem/packet.hh"
45 #include "mem/request.hh"
46 #include "sim/sim_events.hh"
47 #include "sim/stats.hh"
51 int TESTER_ALLOCATOR
=0;
54 MemTest::CpuPort::recvTiming(PacketPtr pkt
)
56 if (pkt
->isResponse()) {
57 memtest
->completeRequest(pkt
);
59 // must be snoop upcall
60 assert(pkt
->isRequest());
61 assert(pkt
->getDest() == Packet::Broadcast
);
67 MemTest::CpuPort::recvAtomic(PacketPtr pkt
)
69 // must be snoop upcall
70 assert(pkt
->isRequest());
71 assert(pkt
->getDest() == Packet::Broadcast
);
76 MemTest::CpuPort::recvFunctional(PacketPtr pkt
)
78 //Do nothing if we see one come through
79 // if (curTick != 0)//Supress warning durring initialization
80 // warn("Functional Writes not implemented in MemTester\n");
81 //Need to find any response values that intersect and update
86 MemTest::CpuPort::recvStatusChange(Status status
)
88 if (status
== RangeChange
) {
89 if (!snoopRangeSent
) {
90 snoopRangeSent
= true;
91 sendStatusChange(Port::RangeChange
);
96 panic("MemTest doesn't expect recvStatusChange callback!");
100 MemTest::CpuPort::recvRetry()
106 MemTest::sendPkt(PacketPtr pkt
) {
108 cachePort
.sendAtomic(pkt
);
109 completeRequest(pkt
);
111 else if (!cachePort
.sendTiming(pkt
)) {
112 DPRINTF(MemTest
, "accessRetry setting to true\n");
115 // dma requests should never be retried
118 panic("Nacked DMA requests are not supported\n");
124 dmaOutstanding
= true;
130 MemTest::MemTest(const Params
*p
)
133 cachePort("test", this),
134 funcPort("functional", this),
136 // mainMem(main_mem),
137 // checkMem(check_mem),
138 size(p
->memory_size
),
139 percentReads(p
->percent_reads
),
140 percentFunctional(p
->percent_functional
),
141 percentUncacheable(p
->percent_uncacheable
),
142 issueDmas(p
->issue_dmas
),
143 progressInterval(p
->progress_interval
),
144 nextProgressMessage(p
->progress_interval
),
145 percentSourceUnaligned(p
->percent_source_unaligned
),
146 percentDestUnaligned(p
->percent_dest_unaligned
),
147 maxLoads(p
->max_loads
),
152 cmd
.push_back("/bin/ls");
153 vector
<string
> null_vec
;
154 // thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
157 cachePort
.snoopRangeSent
= false;
158 funcPort
.snoopRangeSent
= true;
160 id
= TESTER_ALLOCATOR
++;
162 // Needs to be masked off once we know the block size.
163 traceBlockAddr
= p
->trace_addr
;
164 baseAddr1
= 0x100000;
165 baseAddr2
= 0x400000;
166 uncacheAddr
= 0x800000;
169 noResponseCycles
= 0;
171 schedule(tickEvent
, 0);
174 dmaOutstanding
= false;
178 MemTest::getPort(const std::string
&if_name
, int idx
)
180 if (if_name
== "functional")
182 else if (if_name
== "test")
185 panic("No Such Port\n");
191 // By the time init() is called, the ports should be hooked up.
192 blockSize
= cachePort
.peerBlockSize();
193 blockAddrMask
= blockSize
- 1;
194 traceBlockAddr
= blockAddr(traceBlockAddr
);
196 // initial memory contents for both physical memory and functional
197 // memory should be 0; no need to initialize them.
202 MemTest::completeRequest(PacketPtr pkt
)
204 Request
*req
= pkt
->req
;
207 dmaOutstanding
= false;
210 DPRINTF(MemTest
, "completing %s at address %x (blk %x)\n",
211 pkt
->isWrite() ? "write" : "read",
212 req
->getPaddr(), blockAddr(req
->getPaddr()));
214 MemTestSenderState
*state
=
215 dynamic_cast<MemTestSenderState
*>(pkt
->senderState
);
217 uint8_t *data
= state
->data
;
218 uint8_t *pkt_data
= pkt
->getPtr
<uint8_t>();
220 //Remove the address from the list of outstanding
221 std::set
<unsigned>::iterator removeAddr
=
222 outstandingAddrs
.find(req
->getPaddr());
223 assert(removeAddr
!= outstandingAddrs
.end());
224 outstandingAddrs
.erase(removeAddr
);
227 if (memcmp(pkt_data
, data
, pkt
->getSize()) != 0) {
228 panic("%s: read of %x (blk %x) @ cycle %d "
229 "returns %x, expected %x\n", name(),
230 req
->getPaddr(), blockAddr(req
->getPaddr()), curTick
,
237 if (numReads
== (uint64_t)nextProgressMessage
) {
238 ccprintf(cerr
, "%s: completed %d read accesses @%d\n",
239 name(), numReads
, curTick
);
240 nextProgressMessage
+= progressInterval
;
243 if (maxLoads
!= 0 && numReads
>= maxLoads
)
244 exitSimLoop("maximum number of loads reached");
246 assert(pkt
->isWrite());
250 noResponseCycles
= 0;
260 using namespace Stats
;
263 .name(name() + ".num_reads")
264 .desc("number of read accesses completed")
268 .name(name() + ".num_writes")
269 .desc("number of write accesses completed")
273 .name(name() + ".num_copies")
274 .desc("number of copy accesses completed")
281 if (!tickEvent
.scheduled())
282 schedule(tickEvent
, curTick
+ ticks(1));
284 if (++noResponseCycles
>= 500000) {
286 cerr
<< "DMA tester ";
288 cerr
<< name() << ": deadlocked at cycle " << curTick
<< endl
;
292 if (accessRetry
|| (issueDmas
&& dmaOutstanding
)) {
293 DPRINTF(MemTest
, "MemTester waiting on accessRetry or DMA response\n");
298 unsigned cmd
= random() % 100;
299 unsigned offset
= random() % size
;
300 unsigned base
= random() % 2;
301 uint64_t data
= random();
302 unsigned access_size
= random() % 4;
303 bool uncacheable
= (random() % 100) < percentUncacheable
;
305 unsigned dma_access_size
= random() % 4;
307 //If we aren't doing copies, use id as offset, and do a false sharing
309 //We can eliminate the lower bits of the offset, and then use the id
310 //to offset within the blks
311 offset
= blockAddr(offset
);
316 Request
*req
= new Request();
317 Request::Flags flags
;
321 flags
.set(Request::UNCACHEABLE
);
322 paddr
= uncacheAddr
+ offset
;
324 paddr
= ((base
) ? baseAddr1
: baseAddr2
) + offset
;
326 bool do_functional
= (random() % 100 < percentFunctional
) && !uncacheable
;
329 paddr
&= ~((1 << dma_access_size
) - 1);
330 req
->setPhys(paddr
, 1 << dma_access_size
, flags
);
331 req
->setThreadContext(id
,0);
333 paddr
&= ~((1 << access_size
) - 1);
334 req
->setPhys(paddr
, 1 << access_size
, flags
);
335 req
->setThreadContext(id
,0);
337 assert(req
->getSize() == 1);
339 uint8_t *result
= new uint8_t[8];
341 if (cmd
< percentReads
) {
344 // For now we only allow one outstanding request per address
345 // per tester This means we assume CPU does write forwarding
346 // to reads that alias something in the cpu store buffer.
347 if (outstandingAddrs
.find(paddr
) != outstandingAddrs
.end()) {
353 outstandingAddrs
.insert(paddr
);
355 // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
356 funcPort
.readBlob(req
->getPaddr(), result
, req
->getSize());
359 "id %d initiating %sread at addr %x (blk %x) expecting %x\n",
360 id
, do_functional
? "functional " : "", req
->getPaddr(),
361 blockAddr(req
->getPaddr()), *result
);
363 PacketPtr pkt
= new Packet(req
, MemCmd::ReadReq
, Packet::Broadcast
);
365 pkt
->dataDynamicArray(new uint8_t[req
->getSize()]);
366 MemTestSenderState
*state
= new MemTestSenderState(result
);
367 pkt
->senderState
= state
;
370 cachePort
.sendFunctional(pkt
);
371 completeRequest(pkt
);
378 // For now we only allow one outstanding request per addreess
379 // per tester. This means we assume CPU does write forwarding
380 // to reads that alias something in the cpu store buffer.
381 if (outstandingAddrs
.find(paddr
) != outstandingAddrs
.end()) {
387 outstandingAddrs
.insert(paddr
);
389 DPRINTF(MemTest
, "initiating %swrite at addr %x (blk %x) value %x\n",
390 do_functional
? "functional " : "", req
->getPaddr(),
391 blockAddr(req
->getPaddr()), data
& 0xff);
393 PacketPtr pkt
= new Packet(req
, MemCmd::WriteReq
, Packet::Broadcast
);
395 uint8_t *pkt_data
= new uint8_t[req
->getSize()];
396 pkt
->dataDynamicArray(pkt_data
);
397 memcpy(pkt_data
, &data
, req
->getSize());
398 MemTestSenderState
*state
= new MemTestSenderState(result
);
399 pkt
->senderState
= state
;
401 funcPort
.writeBlob(req
->getPaddr(), pkt_data
, req
->getSize());
404 cachePort
.sendFunctional(pkt
);
405 completeRequest(pkt
);
415 if (cachePort
.sendTiming(retryPkt
)) {
416 DPRINTF(MemTest
, "accessRetry setting to false\n");
424 MemTest::printAddr(Addr a
)
426 cachePort
.printAddr(a
);
431 MemTestParams::create()
433 return new MemTest(this);