src/cpu/testers/rubytest/RubyTester.cc

   1 /*
   2  * Copyright (c) 2012-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  15  * Copyright (c) 2009 Advanced Micro Devices, Inc.
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #include "base/misc.hh"
  43 #include "cpu/testers/rubytest/Check.hh"
  44 #include "cpu/testers/rubytest/RubyTester.hh"
  45 #include "debug/RubyTest.hh"
  46 #include "mem/ruby/common/Global.hh"
  47 #include "mem/ruby/common/SubBlock.hh"
  48 #include "mem/ruby/system/System.hh"
  49 #include "sim/sim_exit.hh"
  50 #include "sim/system.hh"
  51
  52 RubyTester::RubyTester(const Params *p)
  53   : MemObject(p), checkStartEvent(this),
  54     _masterId(p->system->getMasterId(name())),
  55     m_checkTable_ptr(nullptr),
  56     m_num_cpus(p->num_cpus),
  57     m_checks_to_complete(p->checks_to_complete),
  58     m_deadlock_threshold(p->deadlock_threshold),
  59     m_num_writers(0),
  60     m_num_readers(0),
  61     m_wakeup_frequency(p->wakeup_frequency),
  62     m_check_flush(p->check_flush),
  63     m_num_inst_ports(p->port_cpuInstPort_connection_count)
  64 {
  65     m_checks_completed = 0;
  66
  67     //
  68     // Create the requested inst and data ports and place them on the
  69     // appropriate read and write port lists.  The reason for the subtle
  70     // difference between inst and data ports vs. read and write ports is
  71     // from the tester's perspective, it only needs to know whether a port
  72     // supports reads (checks) or writes (actions).  Meanwhile, the protocol
  73     // controllers have data ports (support read and writes) or inst ports
  74     // (support only reads).
  75     // Note: the inst ports are the lowest elements of the readPort vector,
  76     // then the data ports are added to the readPort vector
  77     //
  78     for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) {
  79         readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i),
  80                                         this, i));
  81     }
  82     for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) {
  83         CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i),
  84                                     this, i);
  85         readPorts.push_back(port);
  86         writePorts.push_back(port);
  87     }
  88
  89     // add the check start event to the event queue
  90     schedule(checkStartEvent, 1);
  91 }
  92
  93 RubyTester::~RubyTester()
  94 {
  95     delete m_checkTable_ptr;
  96     // Only delete the readPorts since the writePorts are just a subset
  97     for (int i = 0; i < readPorts.size(); i++)
  98         delete readPorts[i];
  99 }
 100
 101 void
 102 RubyTester::init()
 103 {
 104     assert(writePorts.size() > 0 && readPorts.size() > 0);
 105
 106     m_last_progress_vector.resize(m_num_cpus);
 107     for (int i = 0; i < m_last_progress_vector.size(); i++) {
 108         m_last_progress_vector[i] = Cycles(0);
 109     }
 110
 111     m_num_writers = writePorts.size();
 112     m_num_readers = readPorts.size();
 113
 114     m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this);
 115 }
 116
 117 BaseMasterPort &
 118 RubyTester::getMasterPort(const std::string &if_name, PortID idx)
 119 {
 120     if (if_name != "cpuInstPort" && if_name != "cpuDataPort") {
 121         // pass it along to our super class
 122         return MemObject::getMasterPort(if_name, idx);
 123     } else {
 124         if (if_name == "cpuInstPort") {
 125             if (idx > m_num_inst_ports) {
 126                 panic("RubyTester::getMasterPort: unknown inst port idx %d\n",
 127                       idx);
 128             }
 129             //
 130             // inst ports directly map to the lowest readPort elements
 131             //
 132             return *readPorts[idx];
 133         } else {
 134             assert(if_name == "cpuDataPort");
 135             //
 136             // add the inst port offset to translate to the correct read port
 137             // index
 138             //
 139             int read_idx = idx + m_num_inst_ports;
 140             if (read_idx >= static_cast<PortID>(readPorts.size())) {
 141                 panic("RubyTester::getMasterPort: unknown data port idx %d\n",
 142                       idx);
 143             }
 144             return *readPorts[read_idx];
 145         }
 146     }
 147 }
 148
 149 bool
 150 RubyTester::CpuPort::recvTimingResp(PacketPtr pkt)
 151 {
 152     // retrieve the subblock and call hitCallback
 153     RubyTester::SenderState* senderState =
 154         safe_cast<RubyTester::SenderState*>(pkt->senderState);
 155     SubBlock& subblock = senderState->subBlock;
 156
 157     tester->hitCallback(id, &subblock);
 158
 159     // Now that the tester has completed, delete the senderState
 160     // (includes sublock) and the packet, then return
 161     delete pkt->senderState;
 162     delete pkt->req;
 163     delete pkt;
 164     return true;
 165 }
 166
 167 bool
 168 RubyTester::isInstReadableCpuPort(int idx)
 169 {
 170     return idx < m_num_inst_ports;
 171 }
 172
 173 MasterPort*
 174 RubyTester::getReadableCpuPort(int idx)
 175 {
 176     assert(idx >= 0 && idx < readPorts.size());
 177
 178     return readPorts[idx];
 179 }
 180
 181 MasterPort*
 182 RubyTester::getWritableCpuPort(int idx)
 183 {
 184     assert(idx >= 0 && idx < writePorts.size());
 185
 186     return writePorts[idx];
 187 }
 188
 189 void
 190 RubyTester::hitCallback(NodeID proc, SubBlock* data)
 191 {
 192     // Mark that we made progress
 193     m_last_progress_vector[proc] = curCycle();
 194
 195     DPRINTF(RubyTest, "completed request for proc: %d\n", proc);
 196     DPRINTF(RubyTest, "addr: 0x%x, size: %d, data: ",
 197             data->getAddress(), data->getSize());
 198     for (int byte = 0; byte < data->getSize(); byte++) {
 199         DPRINTF(RubyTest, "%d", data->getByte(byte));
 200     }
 201     DPRINTF(RubyTest, "\n");
 202
 203     // This tells us our store has 'completed' or for a load gives us
 204     // back the data to make the check
 205     Check* check_ptr = m_checkTable_ptr->getCheck(data->getAddress());
 206     assert(check_ptr != NULL);
 207     check_ptr->performCallback(proc, data, curCycle());
 208 }
 209
 210 void
 211 RubyTester::wakeup()
 212 {
 213     if (m_checks_completed < m_checks_to_complete) {
 214         // Try to perform an action or check
 215         Check* check_ptr = m_checkTable_ptr->getRandomCheck();
 216         assert(check_ptr != NULL);
 217         check_ptr->initiate();
 218
 219         checkForDeadlock();
 220
 221         schedule(checkStartEvent, curTick() + m_wakeup_frequency);
 222     } else {
 223         exitSimLoop("Ruby Tester completed");
 224     }
 225 }
 226
 227 void
 228 RubyTester::checkForDeadlock()
 229 {
 230     int size = m_last_progress_vector.size();
 231     Cycles current_time = curCycle();
 232     for (int processor = 0; processor < size; processor++) {
 233         if ((current_time - m_last_progress_vector[processor]) >
 234                 m_deadlock_threshold) {
 235             panic("Deadlock detected: current_time: %d last_progress_time: %d "
 236                   "difference:  %d processor: %d\n",
 237                   current_time, m_last_progress_vector[processor],
 238                   current_time - m_last_progress_vector[processor], processor);
 239         }
 240     }
 241 }
 242
 243 void
 244 RubyTester::print(std::ostream& out) const
 245 {
 246     out << "[RubyTester]" << std::endl;
 247 }
 248
 249 RubyTester *
 250 RubyTesterParams::create()
 251 {
 252     return new RubyTester(this);
 253 }